Controlling subnanometer gaps in plasmonic dimers using graphene.

Graphene is used as the thinnest possible spacer between gold nanoparticles and a gold substrate. This creates a robust, repeatable, and stable subnanometer gap for massive plasmonic field enhancements. White light spectroscopy of single 80 nm gold nanoparticles reveals plasmonic coupling between the particle and its image within the gold substrate. While for a single graphene layer, spectral doublets from coupled dimer modes are observed shifted into the near-infrared, these disappear for increasing numbers of layers. These doublets arise from charger-transfer-sensitive gap plasmons, allowing optical measurement to access out-of-plane conductivity in such layered systems. Gating the graphene can thus directly produce plasmon tuning.

Input/output pulse operation of ZnO nanowire threshold integrators.

Integrating more functionality into individual nano-components is a key step to exploit alternative architectures for energy-efficient computation, such as, for instance, neuromorphic computing. Here, we show how to configure ZnO nanowire field-effect transistors as light pulse integrators with programmable threshold. We demonstrate that these single-component devices can be operated as both synchronous and asynchronous neuron-like structures, where the firing threshold and the form of the output signal, either step-like or spiked, can be controlled by using several operational parameters, including the environment in which the device operates. A detailed study showing how environmental variables, such as relative humidity, ambient light and temperature, affect device operation is presented.

High pressure Raman scattering of silicon nanowires.

We study the high pressure response, up to 8 GPa, of silicon nanowires (SiNWs) with ∼ 15 nm diameter, by Raman spectroscopy. The first order Raman peak shows a superlinear trend, more pronounced compared to bulk Si. Combining transmission electron microscopy and Raman measurements we estimate the SiNWs' bulk modulus and the Grüneisen parameters. We detect an increase of Raman linewidth at ∼ 4 GPa, and assign it to pressure induced activation of a decay process into LO and TA phonons. This pressure is smaller compared to the ∼ 7 GPa reported for bulk Si. We do not observe evidence of phase transitions, such as discontinuities or change in the pressure slopes, in the investigated pressure range.

Optical characterization of oxide encapsulated silicon nanowires of various morphologies.

The optical properties of four different silicon nanowire structures were investigated. Two of the samples consisted of spheres of nanocrystalline silicon en-capsulated by silicon oxide nanowires, with other two consisting of crystalline silicon nanowires coated by silicon oxide shells. The nanostructures produced by oxide assisted growth consisted of spheres of crystalline silicon encapsulated by silicon oxide shells. The absorption and photoluminescence of the different structures of the sample are investigated. The emitting species responsible for photoluminescence across the visible spectrum are discussed.

Compound Quantum Dot-Perovskite Optical Absorbers on Graphene Enhancing Short-Wave Infrared Photodetection.

Colloidal quantum dots (QDs) combined with a graphene charge transducer promise to provide a photoconducting platform with high quantum efficiency and large intrinsic gain, yet compatible with cost-efficient polymer substrates. The response time in these devices is limited, however, and fast switching is only possible by sacrificing the high sensitivity. Furthermore, tuning the QD size toward infrared absorption using conventional organic capping ligands progressively reduces the device performance characteristics. Here we demonstrate methods to couple large QDs (>6 nm in diameter) with organometal halide perovskites, enabling hybrid graphene phototransistor arrays on plastic foils that simultaneously exhibit a specific detectivity of 5 × 1012 Jones and high video-frame-rate performance. PbI2 and CH3NH3I co-mediated ligand exchange in PbS QDs improves surface passivation and facilitates electronic transport, yielding faster charge recovery, whereas PbS QDs embedded into a CH3NH3PbI3 matrix produce spatially separated photocarriers leading to large gain.

Self-aligned coupled nanowire transistor.

The integration of multiple functionalities into individual nanoelectronic components is increasingly explored as a means to step up computational power, or for advanced signal processing. Here, we report the fabrication of a coupled nanowire transistor, a device where two superimposed high-performance nanowire field-effect transistors capable of mutual interaction form a thyristor-like circuit. The structure embeds an internal level of signal processing, showing promise for applications in analogue computation. The device is naturally derived from a single NW via a self-aligned fabrication process.

Top-gated silicon nanowire transistors in a single fabrication step.

Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.

Nanowire lithography on silicon.

Nanowire lithography (NWL) uses nanowires (NWs), grown and assembled by chemical methods, as etch masks to transfer their one-dimensional morphology to an underlying substrate. Here, we show that SiO2 NWs are a simple and compatible system to implement NWL on crystalline silicon and fabricate a wide range of architectures and devices. Planar field-effect transistors made of a single SOI-NW channel exhibit a contact resistance below 20 kOmega and scale with the channel width. Further, we assess the electrical response of NW networks obtained using a mask of SiO2 NWs ink-jetted from solution. The resulting conformal network etched into the underlying wafer is monolithic, with single-crystalline bulk junctions; thus no difference in conductivity is seen between a direct NW bridge and a percolating network. We also extend the potential of NWL into the third dimension, by using a periodic undercutting that produces an array of vertically stacked NWs from a single NW mask.

Ion beam doping of silicon nanowires.

We demonstrate n- and p-type field-effect transistors based on Si nanowires (SiNWs) implanted with P and B at fluences as high as 10(15) cm (-2). Contrary to what would happen in bulk Si for similar fluences, in SiNWs this only induces a limited amount of amorphization and structural disorder, as shown by electrical transport and Raman measurements. We demonstrate that a fully crystalline structure can be recovered by thermal annealing at 800 degrees C. For not-annealed, as-implanted NWs, we correlate the onset of amorphization with an increase of phonon confinement in the NW core. This is ion-dependent and detectable for P-implantation only. Hysteresis is observed following both P and B implantation.