High-bandwidth light inputting multilevel photoelectric memory based on thin-film transistor with a floating gate of CsPbBr3/CsPbI3 blend quantum dots.

The electronic-photonic convergent systems can overcome the data transmission bottleneck for microchips by enabling processor and memory chips with high-bandwidth optical input/output. However, current silicon-based electronic-photonic systems require various functional devices/components to convert high-bandwidth optical signals into electrical ones, thus making further integrations of sophisticated systems rather difficult. Here, we demonstrate thin-film transistor-based photoelectric memories employing CsPbBr3/CsPbI3 blend perovskite quantum dots (PQDs) as a floating gate, and multilevel memory cells are achieved under programming and erasing modes, respectively, by imputing high-bandwidth optical signals. For different bandwidth light input (i.e. 500-550, 575-650 and 675-750 nm) with the same intensity, three levels of programming window (i.e. 3.7, 1.9 and 0.8 V) and erasing window (i.e. -1.9, -0.6 and -0.1 V) are obtained under electrical pulses, respectively. This is because the blend PQDs have two different bandgaps, and different amounts of photo-generated carriers can be produced for different wavelength optical inputs. It is noticed that the 675-750 nm light inputs have no effects on both programming and erasing windows because of no photo-carriers generation. Four memory states are demonstrated, showing enough large gaps (1.12-5.61 V) between each other, good data retention and programming/erasing endurance. By inputting different optical signals, different memory states can be switched easily. Therefore, this work directly demonstrates high-bandwidth light inputting multilevel memory cells for novel electronic-photonic systems.

Voltage-Polarity Dependent Programming Behaviors of Amorphous In-Ga-Zn-O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer.

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 µs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as -6.5 V for a gate bias pulse of -13 V/1 µs. In the case of 12 V/1 ms programming (P) and -12 V/10 µs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO +) and doubly ionized oxygen vacancy (VO 2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.