Controlling the Electrical Transport Properties of Nanocontacts to Nanowires.

The ability to control the properties of electrical contacts to nanostructures is essential to realize operational nanodevices. Here, we show that the electrical behavior of the nanocontacts between free-standing ZnO nanowires and the catalytic Au particle used for their growth can switch from Schottky to Ohmic depending on the size of the Au particles in relation to the cross-sectional width of the ZnO nanowires. We observe a distinct Schottky to Ohmic transition in transport behavior at an Au to nanowire diameter ratio of 0.6. The current-voltage electrical measurements performed with a multiprobe instrument are explained using 3-D self-consistent electrostatic and transport simulations revealing that tunneling at the contact edge is the dominant carrier transport mechanism for these nanoscale contacts. The results are applicable to other nanowire materials such as Si, GaAs, and InAs when the effects of surface charge and contact size are considered.

Thickness Effect on the Solid-State Reaction of a Ni/GaAs System.

Ni thin films with different thicknesses were grown on a GaAs substrate using the magnetron sputtering technique followed by in situ X-ray diffraction (XRD) annealing in order to study the solid-state reaction between Ni and GaAs substrate. The thickness dependence on the formation of the intermetallic phases was investigated using in situ and ex situ XRD, pole figures, and atom probe tomography (APT). The results indicate that the 20 nm-thick Ni film exhibits an epitaxial relation with the GaAs substrate, which is (001) Ni//(001) GaAs and [111] Ni//[110] GaAs after deposition. Increasing the film's thickness results in a change of the Ni film's texture. This difference has an impact on the formation temperature of Ni3GaAs. This temperature decreases simultaneously with the thickness increase. This is due to the coherent/incoherent nature of the initial Ni/GaAs interface. The Ni3GaAs phase decomposes into the binary and ternary compounds xNiAs and Ni3-xGaAs1-x at about 400 °C. Similarly to Ni3GaAs, the decomposition temperature of the second phase also depends on the initial thickness of the Ni layer.

Special Issue: Nanowire Field-Effect Transistor (FET).

This Special Issue looks at recent developments in the research field of Nanowire Field-Effect Transistors (NW-FETs), covering different aspects of technology, physics, and modelling of these nanoscale devices. In this summary, we present seven outstanding articles on NW-FETs by providing a brief overview of the articles' content.

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs.

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 µA/µm, and an on-current (I ON) of 1770 µA/µm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55 . 5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness.

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando's and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height ([Formula: see text]). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando's model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with [Formula: see text] channel orientation are affected more by the IRS than those with the [Formula: see text] crystal orientation. Finally, Λ and [Formula: see text] are shown to affect the device performance similarly. A change in values by 30% (Λ) or [Formula: see text] ([Formula: see text]) results in an increase (decrease) of up to [Formula: see text] in the drive current.

Nondestructive Method for Mapping Metal Contact Diffusion in In2O3 Thin-Film Transistors.

The channel width-to-length ratio is an important transistor parameter for integrated circuit design. Contact diffusion into the channel during fabrication or operation alters the channel width and this important parameter. A novel methodology combining atomic force microscopy and scanning Kelvin probe microscopy (SKPM) with self-consistent modeling is developed for the nondestructive detection of contact diffusion on active devices. Scans of the surface potential are modeled using physically based Technology Computer Aided Design (TCAD) simulations when the transistor terminals are grounded and under biased conditions. The simulations also incorporate the tip geometry to investigate its effect on the measurements due to electrostatic tip-sample interactions. The method is particularly useful for semiconductor- and metal-semiconductor interfaces where the potential contrast resulting from dopant diffusion is below that usually detectable with scanning probe microscopy.