Improved synaptic functionalities of Li-based nano-ionic synaptic transistor with ultralow conductance enabled by Al2O3barrier layer.

In this study, we investigated the effect of an Al2O3barrier layer in an all-solid-state inorganic Li-based nano-ionic synaptic transistor (LST) with Li3PO4electrolyte/WOxchannel structure. Near-ideal synaptic behavior in the ultralow conductance range (∼50 nS) was obtained by controlling the abrupt ion migration through the introduction of a sputter-deposited thin (∼3 nm) Al2O3interfacial layer. A trade-off relationship between the weight update linearity and on/off ratio with varying Al2O3layer thickness was also observed. To determine the origin of the Al2O3barrier layer effects, cyclic voltammetry analysis was conducted, and the optimal ionic diffusivity and mobility were found to be key parameters in achieving ideal synaptic behavior. Owing to the controlled ion migration, the retention characteristics were considerably improved by the Al2O3barrier. Finally, a highly improved pattern recognition accuracy (83.13%) was achieved using the LST with an Al2O3barrier of optimal thickness.

Titanium-oxide based nanoscale and embeddable subzero temperature sensor using MIT deformation characteristics.

In this research, we propose a nanoscale and embeddable subzero temperature sensor that is made with a temperature-dependent titanium-oxide based metal-insulator-transition (MIT) device. For a nanoscale two-terminal structured MIT device, the MIT device's characteristics are noticeably changed from abrupt to gradual MIT under zero temperature, which is called MIT deformation. On the basis of the MIT deformation characteristics, subzero temperatures can be detected by reading current levels as temperature changes. Furthermore, this sensor has desirable sensing properties such as high-linearity and proper sensitivity. The obtained results strongly show that titanium-oxides with CMOS process compatibility, cost-effectiveness, nontoxicity, etc, can be applied at the nanoscale and embeddable on subzero temperature sensors on a chip.

Microstructural engineering in interface-type synapse device for enhancing linear and symmetric conductance changes.

The origins of the nonlinear and asymmetric synaptic characteristics of TiO x -based synapse devices were investigated. Based on the origins, a microstructural electrode was utilized to improve the synaptic characteristics. Under an identical pulse bias, a TiO x -based synapse device exhibited saturated conductance changes, which led to nonlinear and asymmetric synaptic characteristics. The formation of an interfacial layer between the electrode and TiO x layer, which can limit consecutive oxygen migration and chemical reactions, was considered as the main origin of the conductance saturation behavior. To achieve consecutive oxygen migration and chemical reactions, structural engineering was utilized. The resultant microstructural electrode noticeably improved the synaptic characteristics, including the unsaturated, linear, and symmetric conductance changes. These synaptic characteristics resulted in the recognition accuracy significantly increasing from 38% to 90% in a neural network-based pattern recognition simulation.

Alternative negative weight for simpler hardware implementation of synapse device based neuromorphic system.

Lately, there has been a rapid increase in the use of software-based deep learning neural networks (S-DNN) for the analysis of unstructured data consumption. For implementation of the S-DNN, synapse-device-based hardware DNN (H-DNN) has been proposed as an alternative to typical Von-Neumann structural computing systems. In the H-DNN, various numerical values such as the synaptic weight, activation function, and etc., have to be realized through electrical device or circuit. Among them, the synaptic weight that should have both positive and negative numerical values needs to be implemented in a simpler way. Because the synaptic weight has been expressed by conductance value of the synapse device, it always has a positive value. Therefore, typically, a pair of synapse devices is required to realize the negative weight values, which leads to additional hardware resources such as more devices, higher power consumption, larger area, and increased circuit complexity. Herein, we propose an alternative simpler method to realize the negative weight (named weight shifter) and its hardware implementation. To demonstrate the weight shifter, we investigated its theoretical, numerical, and circuit-related aspects, following which the H-DNN circuit was successfully implemented on a printed circuit board.

Applicability of Aerosol Deposition Process for flexible electronic device and determining the Film Formation Mechanism with Cushioning Effects.

In this paper, we demonstrated the feasibility of the Aerosol Deposition (AD) method which can be adapted as a future fabrication process for flexible electronic devices. On the basis of this method's noticeable advantages such as room-temperature processing, suitability for mass production, wide material selectivity, and direct fabrication on a flexible substrate, we fabricated and evaluated a flexible conductive bridge random access memory (CBRAM) to confirm the feasibility of this method. The CBRAM was fabricated by the AD-method, and a novel film formation mechanism was observed and analyzed. Considering that the analyzed film formation mechanism is notably different with previously reported for film formation mechanisms of the AD method, these results of study will provide strong guidance for the fabrication of flexible electronic device on ductile substrate.