Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes.

The deluge of sensors and data generating devices has driven a paradigm shift in modern computing from arithmetic-logic centric to data-centric processing. Data-centric processing require innovations at the device level to enable novel compute-in-memory (CIM) operations. A key challenge in the construction of CIM architectures is the conflicting trade-off between the performance and their flexibility for various essential data operations. Here, we present a transistor-free CIM architecture that permits storage, search, and neural network operations on sub-50 nm thick Aluminum Scandium Nitride ferroelectric diodes (FeDs). Our circuit designs and devices can be directly integrated on top of Silicon microprocessors in a scalable process. By leveraging the field-programmability, nonvolatility, and nonlinearity of FeDs, search operations are demonstrated with a cell footprint <0.12 µm2 when projected onto 45 nm node technology. We further demonstrate neural network operations with 4-bit operation using FeDs. Our results highlight FeDs as candidates for efficient and multifunctional CIM platforms.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory.

Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

Multistate, Ultrathin, Back-End-of-Line-Compatible AlScN Ferroelectric Diodes.

The growth in data generation necessitates efficient data processing technologies to address the von Neumann bottleneck in conventional computer architecture. Memory-driven computing, which integrates nonvolatile memory (NVM) devices in a 3D stack, is gaining attention, with CMOS back-end-of-line (BEOL)-compatible ferroelectric (FE) diodes being ideal due to their two-terminal design and inherently selector-free nature, facilitating high-density crossbar arrays. Here, we demonstrate BEOL-compatible, high-performance FE diodes scaled to 5, 10, and 20 nm FE Al0.72Sc0.28N/Al0.64Sc0.36N films. Through interlayer (IL) engineering, we show substantial improvements in the on/off ratios (>166 times) and rectification ratios (>176 times) in these scaled devices. These characteristics also enable 5-bit multistate operation with a stable retention. We also experimentally and theoretically demonstrate the counterintuitive result that the inclusion of an IL can lead to a decrease in the ferroelectric switching voltage of the device. An in-depth analysis into the device transport mechanisms is performed, and our compact model aligns seamlessly with the experimental results. Our results suggest the possibility of using scaled AlxSc1-xN FE diodes for high-performance, low-power, embedded NVM.

Tuning Polarity in WSe2/AlScN FeFETs via Contact Engineering.

Recent advancements in ferroelectric field-effect transistors (FeFETs) using two-dimensional (2D) semiconductor channels and ferroelectric Al0.68Sc0.32N (AlScN) allow high-performance nonvolatile devices with exceptional ON-state currents, large ON/OFF current ratios, and large memory windows (MW). However, previous studies have solely focused on n-type FeFETs, leaving a crucial gap in the development of p-type and ambipolar FeFETs, which are essential for expanding their applicability to a wide range of circuit-level applications. Here, we present a comprehensive demonstration of n-type, p-type, and ambipolar FeFETs on an array scale using AlScN and multilayer/monolayer WSe2. The dominant injected carrier type is modulated through contact engineering at the metal-semiconductor junction, resulting in the realization of all three types of FeFETs. The effect of contact engineering on the carrier injection is further investigated through technology-computer-aided design simulations. Moreover, our 2D WSe2/AlScN FeFETs achieve high electron and hole current densities of ∼20 and ∼10 µA/µm, respectively, with a high ON/OFF ratio surpassing ∼107 and a large MW of >6 V (0.14 V/nm).

Nonvolatile Control of Valley Polarized Emission in 2D WSe2-AlScN Heterostructures.

Achieving robust and electrically controlled valley polarization in monolayer transition metal dichalcogenides (ML-TMDs) is a frontier challenge for realistic valleytronic applications. Theoretical investigations show that the integration of 2D materials with ferroelectrics is a promising strategy; however, an experimental demonstration has remained elusive. Here, we fabricate ferroelectric field-effect transistors using a ML-WSe2 channel and an Al0.68Sc0.32N (AlScN) ferroelectric dielectric and experimentally demonstrate efficient tuning as well as non-volatile control of valley polarization. We measure a large array of transistors and obtain a maximum valley polarization of ∼27% at 80 K with stable retention up to 5400 s. The enhancement in the valley polarization is ascribed to the efficient exciton-to-trion (X-T) conversion and its coupling with an out-of-plane electric field, viz., the quantum-confined Stark effect. This changes the valley depolarization pathway from strong exchange interactions to slow spin-flip intervalley scattering. Our research demonstrates a promising approach for achieving non-volatile control over valley polarization for practical valleytronic device applications.

Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors.

Three-dimensional monolithic integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrent with enhanced energy efficiency in big data applications such as artificial intelligence. Despite decades of efforts, there remains an urgent need for reliable, compact, fast, energy-efficient and scalable memory devices. Ferroelectric field-effect transistors (FE-FETs) are a promising candidate, but requisite scalability and performance in a back-end-of-line process have proven challenging. Here we present back-end-of-line-compatible FE-FETs using two-dimensional MoS2 channels and AlScN ferroelectric materials, all grown via wafer-scalable processes. A large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios greater than 107 and ON-current density greater than 250 µA um-1, all at ~80 nm channel length are demonstrated. The FE-FETs show stable retention up to 10 years by extension, and endurance greater than 104 cycles in addition to 4-bit pulse-programmable memory features, thereby opening a path towards the three-dimensional heterointegration of a two-dimensional semiconductor memory with silicon complementary metal-oxide-semiconductor logic.