RESUMO
Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.
RESUMO
Event-driven data acquisition is used to capture information from fast transient phenomena typically requiring a high sampling speed. This is an important requirement in the ITER Neutral Beam Test Facility for the development of one of the heating systems of the ITER nuclear fusion experiment. The Red Pitaya board has been chosen for this project because of its versatility and low cost. Versatility is provided by the hosted Zynq System on Chip (SoC), which allows full configuration of the module architecture and the OpenSource architecture of Red Pitaya. Price is an important factor, because the boards are installed in a hostile environment where devices can be damaged by EMI and radiation. A flexible solution for event-driven data acquisition has been developed in the Zynq SoC and interfaced to the Linux-based embedded ARM processor. It has been successfully adopted in a variety of data acquisition applications in the test facility.
RESUMO
Stable and uniform beams with low divergence are required in particle accelerators; therefore, beyond the accelerated current, measuring the beam current spatial uniformity and stability over time is necessary to assess the beam performance, since these parameters affect the perveance and thus the beam optics. For high-power beams operating with long pulses, it is convenient to directly measure these current parameters with a non-intercepting system due to the heat management requirement. Such a system needs to be capable of operating in a vacuum in the presence of strong electromagnetic fields and overvoltages, due to electrical breakdowns in the accelerator. Finally, the measure of the beam current needs to be efficiently integrated into a pulse file with the other relevant plant parameters to allow the data analyses required for beam optimization. This paper describes the development, design and commissioning of such a non-intercepting system, the so-called beamlet current monitor (BCM), aimed to directly measure the electric current of a particle beam. In particular, the layout of the system was adapted to the SPIDER experiment, the ion source (IS) prototype of the heating neutral beam injectors (HNB) for the ITER fusion reactor. The diagnostic is suitable to provide the electric current of five beamlets from DC up to 10 MHz.