RESUMO
This paper presents a 5G new radio (NR) FR2 beamforming system with an integrated transceiver module. A real-time operating module providing enhanced flexibility and capability has been proposed. The integrated RF beamforming system with an integrated transceiver module can be operated in 8Tx-8Rx mode configuration simultaneously. A series-fed structure 8 × 7 microstrip antenna array for compact size and improved directivity is employed in the RF beamforming module. The RF beamforming module incorporates a custom 28 GHz, eight-channel fully differential beamforming IC (BFIC). An eight-channel BFIC in a phased-array beamforming system offers advantages in terms of increased antenna density and improved beam steering precision. The RF beamforming module is integrated with an RF transceiver module that enables the simultaneous up-conversion and down-conversion of the baseband signal. The RF transmitter module consists of a transmitter, a receiver, a signal generator, a power supply, and a control unit. The RF beamforming system can scan horizontally from -50° to +50° with a step of 10°. To achieve an optimized beam pattern, a calibration was conducted. The transmit and receive conversion gain of around 20 dB is achieved with the transceiver module. To verify the communication performance of the manufactured integrated RF beamforming system, a real-time wireless video transmission/reception test was performed at a frequency of 28 GHz, and the video file was transmitted smoothly in real time without interruption within a range of ±50°.
RESUMO
The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP's ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.