A neural-network packet switch controller: scalability, performance, and network optimization.

We examine a novel combination of architecture and algorithm for a packet switch controller that incorporates an experimentally implemented optically interconnected neural network. The network performs scheduling decisions based on incoming packet requests and priorities. We show how and why, by means of simulation, the move from a continuous to a discrete algorithm has improved both network performance and scalability. The system's limitations are examined and conclusions drawn as to its maximum scalability and throughput based on today's technologies.

Tolerance analysis of cascaded self-electro-optic-effect-device arrays.

In constructing symmetric self-electro-optic-effect-device-based, two-dimensional information processing circuits, it is necessary to know the nonuniformity that can be tolerated of the reflectivity responses of the arrays of devices. It is also necessary to know the allowable nonuniformity of the passive optical components used to direct beam arrays onto and between the active symmetric self-electro-optic-effect devices. A method for determining the mutual tolerances is presented with examples of the volumes of acceptable operation in the parameter space of the circuits. Leakage between devices is considered, which leads to acceptable regimes for those parameters that can be adjusted once the circuit has been constructed and to narrower regimes in which high clock and cycle rates can be achieved.

Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting.

The performance factors associated with self-electro-optic-effect-device-(SEED-) based smart-pixel arrays are analyzed in terms of semiconductor technology and pixel complexity. The sorting task is chosen as a practical example. Complementary metal-oxide semiconductor (CMOS)-SEED 2 × 2 self-routing nodes operated with quasi-cw-mode lasers are shown to provide the maximum processing power and on- or off-chip communication rate. The need for new front-end amplifiers for the smart-pixel technology is emphasized.

Optoelectronic neural-network scheduler for packet switches.

A novel, to our knowledge, type of packet scheduler that could significantly outperform current state-of-the-art schedulers is presented. The operation and the design of such a scheduler are discussed, and a fully operational experimental implementation is described. The scheduler uses a neural network in a winner-take-all strategy to optimize decisions on the throughput of both a crossbar and a banyan switching fabric. The problems of high interconnection density are solved by use of a free-space optical interconnect that exploits diffractive optical techniques to generate the required interconnection patterns and weights.