Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire.

A Si/Ge hetero tunnel field-effect transistor (TFET) with junctionless channel based on nanowire (JLNW-TFET) is proposed, and its electrical performance and dependency of natural parameters are investigated. The JLNW-TFET is operated by compensating each demerit of the following two mechanisms: thermionic generation of junctionless field-effect transistor (JLFET) and band to band tunneling (BTBT) generation of tunnel field-effect transistor (TFET). Although the on-current Ion of JLNW-TFET decreases approximately ten times as much as that of the conventional TFET, its subthreshold swing SS is three times steeper than that of the conventional TFET and ambipolar current Iambipolar does not appear as a result of the structural characteristics. Ioff increases due to Shockley-Read-Hall (SRH) recombination when the density of traps increases; however, an increase in SS is not observed. At temperatures higher than room temperature, Ioff increases slightly and SS and Ion are almost constant. Furthermore, quantum confinement and trap assisted tunneling do not significantly affect the performance of the devices except for increasing Ioff and slightly decreasing Ion.

Investigation of Corner Effect and Identification of Tunneling Regimes in L-Shaped Tunnel Field-Effect-Transistor.

Corner-effect existing in L-shaped tunnel field-effect-transistor (LTFET) was investigated using numerical simulations and band diagram analysis. It was found that the corner-effect is caused by the convergence of electric field in the sharp source corner present in an LTFET, thereby increasing the electric field in the sharp source corner region. It was found that in the corner-effect region tunneling starts early, as a function of applied bias, as compared to the rest of the channel not affected by corner-effect. Further, different tunneling regimes as a function of applied bias were identified in the LTFET including source to channel and channel to channel tunneling regimes. Presence of different tunneling regimes in LTFET was analytically justified with a set of equations developed to model source to channel, and channel to channel tunneling currents. Drain-current-gate-voltage (Ids-Vgs) characteristics obtained from the equations is in reasonable qualitative agreement with numerical simulation.

Electrical Characteristics of Ge/Si-Based Source Pocket Tunnel Field-Effect Transistors.

Two types of Ge/Si-based novel tunnel field-effect transistors (TFETs) with source pockets are proposed. In the proposed Ge/Si-based TFETs, the materials in the source, channel, and drain are Ge, Si, and Si, respectively, and the gate shortly overlaps the source. One of the proposed TFETs has an intrinsic Ge pocket and the other has an intrinsic Si pocket, shallowly doped in the source region below the source-overlapped gate. The current-voltage (I-V) characteristics of the proposed Ge/Si-based TFETs were simulated using the TCAD device simulator, and were compared with those of Si, Ge, and Ge (in source)/Si (in channel and drain) TFETs. The on-currents (ION) of the proposed Ge/Si-based TFETs and Ge-TFET were higher, but the subthreshold swing (SS) of the Ge/Si-based TFET with the Ge source pocket was the worst, owing to the hump effect. The off-current (IOFF) of the Ge-based TFET was the worst, but those of the other devices were the same because their drain material was Si, with a larger band gap than Ge. The SS of the proposed Ge/Si-based TFET with a Si source pocket was the best, because the tunneling length of the Ge/Si heterojunction was the shortest, as shown by the simulated energy band. Defect-induce degradation due to large lattice mismatch between Si and Ge materials is investigated including the trap-assisted-tunneling (TAT) model. Overall, the proposed Ge/Si-based TFET with a Si source pocket demonstrated the best performance.

Work-Function Engineering of Source-Overlapped Dual-Gate Tunnel Field-Effect Transistor.

A source-overlapped dual-material gate TFET (SODM-TFET), which features different materials in its source-overlapped and channel gates, is proposed here, and its performance is investigated for various channel and source gate work functions (ψmc and ψms, respectively). Previous studies reported a hump effect in source-overlapped TFETs (SO-TFETs) and relatively high currents in the ambipolar state. The flat-band voltage in our SODM-TFET was controlled by modulating ψms and ψmc, allowing to reduce the hump effect and suppressing the ambipolar current. Compared with conventional SO-TFETs, minimal subthreshold-swing (SSmin) and average SS (SSavg) of our SODM-TFET were ~4 and ~3.5 times lower, respectively. The on/off current ratio (Ion/Ioff) of the SODM-TFET increased by ~100, while the on-current (Ion) of the SODM-TFET increased by ~100 at the supply voltage of 0.7 V.

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD.

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide-nitride-oxide layer and a metal-oxide-semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and -18 V for 1 µs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.

Analytic modeling of a depletion-mode cylindrical surrounding-gate nanowire field-effect transistor.

A compact model for depletion-mode p-type cylindrical surrounding-gate nanowire field-effect transistors (SGNWFETs) is proposed. The SGNWFET model consists of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic SGNWFET. Based on the electrostatic method, the intrinsic SGNWFET model was derived from current conduction mechanisms attributed to bulk charges through the center neutral region, in addition to accumulation charges through the surface accumulation region. The authors' previously developed Schottky diode model was used for the M-S contacts. The new model was applied to an advanced design system (ADS), whereby the intrinsic part of the SGNWFET and the Schottky diode were developed using the Verilog-A language. The results of the simulation of the newly developed SGNWFET model reproduced the experiment results considerably well.

Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor.

In this paper, the tunneling effect for a N-type feedback field-effect transistor (NFBFET) was investigated. The NFBFET has highly doped N-P junction in the channel region. When drain-source voltage is applied at the NFBFET, the aligning between conduction band of N-region and valence band of P-region occur, and band-to-band tunneling (BTBT) current can be formed on surface region of N-P junction in the channel of the NFBFET. When the doping concentration of gated-channel region (Ngc) is 4 × 1018 cm-3, the tunneling current makes off-currents increase approximately 104 times. As gate-source voltage is applied to NFBFET, the tunneling rate decreases owing to reducing of aligned region between bands by stronger gate-field. Eventually, the tunneling currents are vanished at the BTBT vanishing point before threshold voltage. When Ngc increase from 4 × 1018 to 6 × 1018, the tunneling current is generated not only at the surface region but also at the bulk region. Moreover, the tunneling length is shorter at the surface and bulk regions, and hence the leakage currents more increase. The BTBT vanishing point also increases due to increase of tunneling rates at surface and bulk region as Ngc increases.

An Investigation of the Effect of the Work-Function Variation of a Monolithic 3D Inverter Stacked with MOSFETs.

The effect of the work-function variation (WFV) of metal-oxide-semiconductor field-effect transistor (MOSFET) gates on a monolithic 3D inverter (M3DINV) structure is investigated in the current paper. The M3DINV has a structure in which MOSFETs are sequentially stacked. The WFV effect of the top- and bottom-tier gates on the M3DINV is investigated using technology computer-aided design (TCAD) and a Monte-Carlo sampling simulation of TCAD. When the interlayer dielectric thickness (TILD) changes from 5 to 100 nm, electrical parameters, such as the threshold voltage, subthreshold swing, on-current, and off-current of the top-tier N-MOSFET and the parameter changes by the change in gate voltage of the bottom-tier P-MOSFET, are investigated. As TILD decreases below about 30 nm, the means and standard deviations of the electrical parameters rapidly increase. This means that the coupling and its distribution are relatively large in the regime and thus should be well considered for M3D circuit simulation. In addition, due to the increase in standard deviation, the WFV effect of both the top- and bottom-tier MOSFET gates was observed to be greater than those of only the top-tier MOSFET gates and only the bottom-tier MOSFET gates.

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor.

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading 'ON' current decreases. To prevent performance degradation, two ways to compensate for current level were suggested.

Effects of Thermal Treatment on DC Voltage-Driven Color Conversion in Organic Light-Emitting Diode.

A DC voltage-dependent color-tunable organic light-emitting diode (CTOLED) was proposed for lighting applications. The CTOLED consists of six consecutive organic layers: the hole injection layer, the hole transport layer (HTL), two emission layers (EMLs), a hole blocking layer (HBL), and an electron transport layer (ETL). Only one metal-free phthalocyanine (H2Pc) layer with a thickness of 5 nm was employed as the EML in the CTOLED on a green organic light-emitting diode (OLED) structure using tris (8-hydroxyquinoline) aluminum (III) (Alq3). The current density-voltage-luminance characteristics of the CTOLEDs before and after thermal treatment were characterized and analyzed. Several Gaussian peaks were also extracted by multipeak fitting analysis of the electroluminescent spectra. In the CTOLED before thermal treatment, green emission was dominant in the entire voltage range from low to high voltages, and blue and infrared were emitted simultaneously and at relatively low intensities at low and high voltages, respectively. In the CTOLED after thermal treatment, the dominant color conversion from blue to green was observed as the applied voltage increased, and the infrared emission was relatively low over the entire voltage range. By simulating the CTOLED with and without traps at the H2Pc interface using a technology computer-aided design simulator, we observed the following: 1. After thermal treatment, the CTOLED emitted blue light by exciton generation at the H2Pc-HBL interface because of the small electron transport through the H2Pc thin film due to the dramatic reduction of traps in the low-voltage regime. 2. In the high-voltage regime, electrons reaching the HBL were transferred to Alq3 by resonant tunneling in two quantum wells; thus, green light was emitted by exciton generation at the HTL-Alq3 interface.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter.

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors.

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation.

In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

Explicit continuous current-voltage (I-V) models for fully-depleted surrounding-gate MOSFETs (SGMOSFETs) with a finite doping body.

An analytical and continuous dc model for cylindrical doped surrounding-gate MOSFETs (SGMOSFETs) in the fully-depleted regime is presented. Starting from Poisson's equation, an implicit charge equation is derived approximately by a superposition principle with the exact channel potential and the charge equations in the depletion approximation. Also, a new explicit charge equation is derived from the implicit charge equation. The current equations without any charge-sheet approximation are based on the implicit and explicit charge control models, and both of them are valid for all the operation regions (linear, saturation, and subthreshold) and traces the transition between them without any fitting parameters. In the case of the SGMOSFETs with the fully-depleted condition, both of results simulated from the SGMOSFET models reproduce various 3D simulation results within 5% errors.

Dependences of the electrical properties on the diameter and the doping concentration of the Si nanowire field effect transistors with a Schottky metal-semiconductor contact.

A compact model of the current-voltage (I-V) characteristics for the Si nanowire field effect transistor (FET) taking into account dependence of the analytical electrical properties on the diameter and the concentration of the Si nanowire of the FETs with a Schottky metal-semiconductor contact has been proposed. I-V characteristics of the nanowire FETs were analytically calculated by using a quantum drift-diffusion current transport model taking into account an equivalent circuit together with the quantum effect of the Si nanowires and a Schottky model at Schottky barriers. The material parameters dependent on different diameters and concentrations of the Si nanowire were numerically estimated from the physical properties of the Si nanowire. The threshold voltage, the mobility, and the doping density of the Si nanowire and the Schottky barrier height at a metal-Si nanowire heterointerface in the nanowire FET were estimated by using the theoretical model.

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs.

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation.

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm-3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

Metal oxide-graphene field-effect transistor: interface trap density extraction model.

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current-gate voltage relationship Ids-Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance-gate voltage Ctot-Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.