Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.
Annu Int Conf IEEE Eng Med Biol Soc
; 2014: 1626-9, 2014.
Article
em En
| MEDLINE
| ID: mdl-25570284
ABSTRACT
This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.
Texto completo:
1
Coleções:
01-internacional
Base de dados:
MEDLINE
Assunto principal:
Fontes de Energia Elétrica
/
Algoritmos
/
Computadores
/
Interfaces Cérebro-Computador
/
Movimento
Limite:
Humans
Idioma:
En
Ano de publicação:
2014
Tipo de documento:
Article