Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors.

ABSTRACT

The effect of interface traps on InGaAs-based vertical gate-all-around (GAA) tunneling field-effect transistors (TFETs) has been investigated using technology computer-aided design (TCAD) simulation. The interface traps distributed within different energy levels (Et) in the energy bandgap of a semiconductor material exhibit various influences on the device performances. In this work, InGaAs-based TFETs are simulated to analyze the effects on the on-state current (Ion), off-state current (Ioff), threshold voltage (Vth), subthreshold swing (SS), and the ambipolar characteristics according to Et and type of the interface traps. We have confirmed that Ioff and SS are degraded by the interface traps. Further, it can be shown that Ion is mainly affected by the acceptor-like traps and ambipolar behavior is affected by the donor-like traps. All the effects increase as Et becomes closer to the midgap. The effects of the interface traps with gate underlap and overlap at the source-channel region also have been investigated, considering the device fabrication. Additionally, the analysis of the effect of junction trap created at the source-channel junction has been performed.