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Area-Selective Chemical Doping on Solution-Processed MoS2 Thin-Film for Multi-Valued Logic Gates.
Kim, Jihyun; Jung, Myeongjin; Lim, Dong Un; Rhee, Dongjoon; Jung, Sung Hyeon; Cho, Hyung Koun; Kim, Han-Ki; Cho, Jeong Ho; Kang, Joohoon.
Afiliação
  • Kim J; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Jung M; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Lim DU; Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 03722, Republic of Korea.
  • Rhee D; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Jung SH; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Cho HK; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Kim HK; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
  • Cho JH; Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 03722, Republic of Korea.
  • Kang J; School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
Nano Lett ; 22(2): 570-577, 2022 Jan 26.
Article em En | MEDLINE | ID: mdl-34779637
ABSTRACT
Multi-valued logic gates are demonstrated on solution-processed molybdenum disulfide (MoS2) thin films. A simple chemical doping process is added to the conventional transistor fabrication procedure to locally increase the work function of MoS2 by decreasing sulfur vacancies. The resulting device exhibits pseudo-heterojunctions comprising as-processed MoS2 and chemically treated MoS2 (c-MoS2). The energy-band misalignment of MoS2 and c-MoS2 results in a sequential activation of the MoS2 and c-MoS2 channel areas under a gate voltage sweep, which generates a stable intermediate state for ternary operation. Current levels and turn-on voltages for each state can be tuned by modulating the device geometries, including the channel thickness and length. The optimized ternary transistors are incorporated to demonstrate various ternary logic gates, including the inverter, NMIN, and NMAX gates.
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Texto completo: 1 Coleções: 01-internacional Base de dados: MEDLINE Idioma: En Ano de publicação: 2022 Tipo de documento: Article

Texto completo: 1 Coleções: 01-internacional Base de dados: MEDLINE Idioma: En Ano de publicação: 2022 Tipo de documento: Article