Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing.

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (gm,peak) by 50% among 28 devices and achieved 70µSµm-1atVDS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1as well as an off-current below 5 nAµm-1which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device withLg = 80 nm in RTA, which shows an increasedgm,peakup to 149µSµm-1atVDS = -0.5 V as well as a low on-resistance of 4.7 kΩ·µm. The potential of further enhancement ingmvia RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth.

Here we present a method to control the size of the openings in hexagonally organized BCP thin films of poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) by using surface reconstruction. The surface reconstruction is based on selective swelling of the P4VP block in ethanol, and its extraction to the surface of the film, resulting in pores upon drying. We found that the BCP pore diameter increases with ethanol immersion temperature. In our case, the temperature range 18 to 60 °C allowed fine-tuning of the pore size between 14 and 22 nm. A conclusion is that even though the molecular weight of the respective polymer blocks is fixed, the PS-b-P4VP pore diameter can be tuned by controlling temperature during surface reconstruction. These results can be used for BCP-based nanofabrication in general, and for vertical nanowire growth in particular, where high pattern density and diameter control are of importance. Finally, we demonstrate successful growth of indium arsenide InAs vertical nanowires by selective-area metal-organic vapor phase epitaxy (MOVPE), using a silicon nitride mask patterned by the proposed PS-b-P4VP surface reconstruction lithography method.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors.

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices. The best devices reached a point subthreshold swing of 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. An increase in the doping level helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation with the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs.

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si.

III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption. In this work, we present vertical heterostructure InAs/InGaAs nanowire MOSFETs with low off-currents provided by the wider band gap material on the drain side suppressing band-to-band tunneling. We demonstrate vertical III-V MOSFETs achieving off-current below 1 nA/µm while still maintaining on-performance comparable to InAs MOSFETs; therefore, this approach opens a path to address not only high-performance applications but also Internet-of-Things applications that require low off-state current levels.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

Low Leakage-Current InAsSb Nanowire Photodetectors on Silicon.

Axially doped p-i-n InAs0.93Sb0.07 nanowire arrays have been grown on Si substrates and fabricated into photodetectors for shortwave infrared detection. The devices exhibit a leakage current density around 2 mA/cm(2) and a 20% cutoff of 2.3 µm at 300 K. This record low leakage current density for InAsSb based devices demonstrates the suitability of nanowires for the integration of III-V semiconductors with silicon technology.

III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Hard X-ray detection using a single 100 nm diameter nanowire.

Submicron sized sensors could allow higher resolution in X-ray imaging and diffraction measurements, which are ubiquitous for materials science and medicine. We present electrical measurements of a single 100 nm diameter InP nanowire transistor exposed to hard X-rays. The X-ray induced conductance is over 5 orders of magnitude larger than expected from reported data for X-ray absorption and carrier lifetimes. Time-resolved measurements show very long characteristic lifetimes on the order of seconds, tentatively attributed to long-lived traps, which give a strong amplification effect. As a proof of concept, we use the nanowire to directly image an X-ray nanofocus with submicron resolution.

InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.

Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a -3 dB cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.

Electrical properties of GaSb/InAsSb core/shell nanowires.

Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2-3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires. Maximum intrinsic field effect mobilities of 200 and 42 cm(2) Vs(-1) were extracted for the GaSb/InAsSb core/shell and bare-GaSb NWs at room temperature, respectively. The temperature-dependence of the mobility suggests that ionized impurity scattering is the dominant scattering mechanism in bare GaSb while phonon scattering dominates in core/shell nanowires. Top-gated field effect transistors were fabricated based on radial GaSb/InAsSb heterostructure nanowires with shell thicknesses in the range 5-7 nm. The fabricated devices exhibited ambipolar conduction, where the output current was studied as a function of AC gate voltage and frequency. Frequency doubling was experimentally demonstrated up to 20 kHz. The maximum operating frequency was limited by parasitic capacitance associated with the measurement chip geometry.

Diameter-Dependent photocurrent in InAsSb nanowire infrared photodetectors.

Photoconductors using vertical arrays of InAs/InAs(1-x)Sb(x) nanowires with varying Sb composition x have been fabricated and characterized. The spectrally resolved photocurrents are strongly diameter dependent with peaks, which are red-shifted with diameter, appearing for thicker wires. Results from numerical simulations are in good agreement with the experimental data and reveal that the peaks are due to resonant modes that enhance the coupling of light into the wires. Through proper selection of wire diameter, the absorptance can be increased by more than 1 order of magnitude at a specific wavelength compared to a thin planar film with the same amount of material. A maximum 20% cutoff wavelength of 5.7 µm is obtained at 5 K for a wire diameter of 717 nm at a Sb content of x = 0.62, but simulations predict that detection at longer wavelengths can be achieved by increasing the diameter. Furthermore, photodetection in InAsSb nanowire arrays integrated on Si substrates is also demonstrated.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

Synthesis and properties of antimonide nanowires.

Antimonide semiconductors are suitable for low-power electronics and long-wavelength optoelectronic applications. In recent years research on antimonide nanowires has become a rapidly growing field, and nano-materials have promising applications in fundamental physics research, for tunnel field-effect transistors, and long-wavelength detectors. In this review, we give an overview of the field of antimonide nanowires, beginning with a description of the synthesis of these nano-materials. Here we summarize numerous reports on antimonide nanowire growth, with the aim to give an overall picture of the distinctive properties of antimonide nanowire synthesis. Secondly, we review the data on the physical properties and emerging applications for antimonide nanowires, focusing on applications in electronics and optics.

Single InAs/GaSb nanowire low-power CMOS inverter.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Effects of Interface Oxidation on Noise Properties and Performance in III-V Vertical Nanowire Memristors.

Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III-V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning. In this work, we evaluate the role of the IL-oxide directly on InAs vertical nanowires using low-frequency noise characterization. We show that the low-frequency noise or the 1/f-noise in InAs vertical RRAMs can be reduced by more than 3 orders of magnitude by engineering the InAs/high-k interface. We also report that the noise properties of the vertical 1T1R do not degrade significantly after RRAM integration making them attractive to be used in emerging electronic circuits.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor.

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts.

Local geometric control of basic synthesis parameters, such as elemental composition, is important for bottom-up synthesis and top-down device definition on-chip but remains a significant challenge. Here, we propose to use lithographically defined metal stacks for regulating the surface concentrations of freely diffusing synthesis elements on compound semiconductors. This is demonstrated by geometric control of Indium droplet formation on Indium Arsenide surfaces, an important consequence of incongruent evaporation. Lithographic defined Aluminium/Palladium metal patterns induce well-defined droplet-free zones during annealing up to 600 °C, while the metal patterns retain their lateral geometry. Compositional and structural analysis is performed, as well as theoretical modelling. The Pd acts as a sink for free In atoms, lowering their surface concentration locally and inhibiting droplet formation. Al acts as a diffusion barrier altering Pd's efficiency. The behaviour depends only on a few basic assumptions and should be applicable to lithography-epitaxial manufacturing processes of compound semiconductors in general.