A CMOS Current-Mode Vertical-Cavity-Semiconductor-Emitting-Laser Diode Driver for Short-Range LiDAR Sensors.

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2.

BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective.

Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro-metal-insulator-semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal-ferro-insulator-semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance (CFE) is not a lumped capacitance. Therefore, for MFIS negative capacitance (NC) devices, the physical explanation which governs the NDR mechanism needs to be addressed. In this work, for the first time, we present the first principle explanation of the NDR effect in MFIS NC FDSOI. We found that the output current variation with the drain to source voltage (VDS), (i.e.gds) primarily depends upon two parameters: (a)VDSdependent inversion charge gradient (∂n/∂VDS); (b)VDSsensitive electron velocity (∂v/∂VDS), and the combined effect of these two dependencies results in NDR. Further, to mitigate the NDR effect, we proposed the BOX engineered NC FDSOI FET, in which the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2layer. In doing so, the inversion charge in the channel is enhanced by the BOX engineered FE layer, which in turn mitigates the NDR and a nearly zerogdswith a minimal positive slope has been obtained. Through well-calibrated TCAD simulations, by utilizing the obtained positivegds, we also designed aVDSindependent constant current mirror which is an essential part of analog circuits. Furthermore, we discussed the impact of the FE parameter (remanent polarization and coercive field) variation on the device performances. We have also compared the acquired results with existing literature on NC-based devices, which justifies that our proposed structure exhibits complete diminution of NDR, thus enabling its use in analog circuit design.

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros.

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 µs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 µW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.