Nano-patterned dual-layer ITO electrode of high brightness blue light emitting diodes using maskless wet etching.

We propose a dual-layer transparent Indium Tin Oxide (ITO) top electrode scheme and demonstrate the enhancement of the optical output power of GaN-based light emitting diodes (LEDs). The proposed dual-layer structure is composed of a layer with randomly distributed sphere-like nano-patterns obtained solely by a maskless wet etching process and a pre-annealed bottom layer to maintain current spreading of the electrode. It was observed that the surface morphologies and optoelectronic properties are dependent on etching duration. This electrode significantly improves the optical output power of GaN-based LEDs with an enhancement factor of 2.18 at 100 mA without degradation in electrical property when compared to a reference LED.

Design Rule of Electron- and Hole-Selective Contacts for Polycrystalline Silicon-Based Passivating Contact Solar Cells.

A crystalline silicon (c-Si) solar cell with a polycrystalline silicon/SiOx (poly-Si/SiOx) structure, incorporating both electron and hole contacts, is an attractive choice for achieving ideal carrier selectivity and serving as a fundamental component in high-efficiency perovskite/Si tandem and interdigitated back-contact solar cells. However, our understanding of the carrier transport mechanism of hole contacts remains limited owing to insufficient studies dedicated to its investigation. There is also a lack of comparative studies on the poly-Si/SiOx electron and hole contacts for ideal carrier-selective solar cells. Therefore, this study aims to address these knowledge gaps by exploring the relationship among microstructural evolution, dopant in-diffusion, and the resulting carrier transport mechanism in both the electron and hole contacts of poly-Si/SiOx solar cells. Electron (n+ poly-Si/SiOx/substrate)- and hole (p+ poly-Si/SiOx/substrate)-selective passivating contacts are subjected to thermal annealing. Changes in the passivation properties and carrier transport mechanisms of these contacts are investigated during thermal annealing at various temperatures. Notably, the results demonstrate that the passivation properties and carrier transport mechanisms are strongly influenced by the microstructural evolution of the poly-Si/SiOx layer stack and dopant in-diffusion. Furthermore, electron and hole contacts exhibit common behaviors regarding microstructural evolution and dopant in-diffusion. However, the hole contacts exhibit relatively inferior electrical properties overall, mainly because both the SiOx interface and the p+ poly-Si are found to be highly defective. Moreover, boron in the hole contacts diffuses deeper than phosphorus in the electron contacts, resulting in deteriorated carrier collection. The experimental results are also supported by device simulation. Based on these findings, design rules are suggested for both electron and hole contacts, such as using thicker SiOx and/or annealing the solar cell at a temperature not exceeding the critical annealing temperature of the hole contacts.

Fully Bottom-Up Waste-Free Growth of Ultrathin Silicon Wafer via Self-Releasing Seed Layer.

The fabrication of ultrathin silicon wafers at low cost is crucial for advancing silicon electronics toward stretchability and flexibility. However, conventional fabrication techniques are inefficient because they sacrifice a large amount of substrate material. Thus, advanced silicon electronics that have been realized in laboratories cannot move forward to commercialization. Here, a fully bottom-up technique for producing a self-releasing ultrathin silicon wafer without sacrificing any of the substrate is presented. The key to this approach is a self-organized nanogap on the substrate fabricated by plasma-assisted epitaxial growth (plasma-epi) and subsequent hydrogen annealing. The wafer thickness can be independently controlled during the bulk growth after the formation of plasma-epi seed layer. In addition, semiconductor devices are realized using the ultrathin silicon wafer. Given the high scalability of plasma-epi and its compatibility with conventional semiconductor process, the proposed bottom-up wafer fabrication process will open a new route to developing advanced silicon electronics.

Fabrication of monolithic polymer nanofluidic channels using nanowires as sacrificial templates.

We report a facile and reliable method to fabricate polymer-based monolithic nanofluidic channels. The nanochannels are obtained via three main steps: (1) fabrication of nanowire-transistor like structures, which are silver or zinc oxide nanowires horizontally bridging two electrodes made of zinc oxide on SiO(2)/Si substrates; (2) casting and curing polyimide solution on the nanowire structures; and (3) selective etching of the nanowire and electrode templates against the polyimide substrates. This process leads to the production of nanochannels with a diameter down to ∼ 50 nm. Our method is based on nanowires that are chemically synthesized whereas nanopattern fabrication conventionally relies on expensive equipment. Moreover, the polymer nanochannels are fabricated monolithically while a process of bonding two different materials is required in traditional methods where leakage problems are often identified at the interface. Construction of nanofluidic circuitry could be expected in the future based on the current work.