Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer.

Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm(2) above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers.

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 µm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers.

Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 µm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.