Approaching the quantum limit in two-dimensional semiconductor contacts.

The development of next-generation electronics requires scaling of channel material thickness down to the two-dimensional limit while maintaining ultralow contact resistance1,2. Transition-metal dichalcogenides can sustain transistor scaling to the end of roadmap, but despite a myriad of efforts, the device performance remains contact-limited3-12. In particular, the contact resistance has not surpassed that of covalently bonded metal-semiconductor junctions owing to the intrinsic van der Waals gap, and the best contact technologies are facing stability issues3,7. Here we push the electrical contact of monolayer molybdenum disulfide close to the quantum limit by hybridization of energy bands with semi-metallic antimony ([Formula: see text]) through strong van der Waals interactions. The contacts exhibit a low contact resistance of 42 ohm micrometres and excellent stability at 125 degrees Celsius. Owing to improved contacts, short-channel molybdenum disulfide transistors show current saturation under one-volt drain bias with an on-state current of 1.23 milliamperes per micrometre, an on/off ratio over 108 and an intrinsic delay of 74 femtoseconds. These performances outperformed equivalent silicon complementary metal-oxide-semiconductor technologies and satisfied the 2028 roadmap target. We further fabricate large-area device arrays and demonstrate low variability in contact resistance, threshold voltage, subthreshold swing, on/off ratio, on-state current and transconductance13. The excellent electrical performance, stability and variability make antimony ([Formula: see text]) a promising contact technology for transition-metal-dichalcogenide-based electronics beyond silicon.

Understanding the Impact of Contact-Induced Strain on the Electrical Performance of Monolayer WS2 Transistors.

Two-dimensional (2D) electronics require low contact resistance (RC) to approach their fundamental limits. WS2 is a promising 2D semiconductor that is often paired with Ni contacts, but their operation is not well understood considering the nonideal alignment between the Ni work function and the WS2 conduction band. Here, we investigate the effects of contact size on nanoscale monolayer WS2 transistors and uncover that Ni contacts impart stress, which affects the WS2 device performance. The strain applied to the WS2 depends on contact size, where long (1 µm) contacts (RC ≈ 1.7 kΩ·µm) show a 78% reduction in RC compared to shorter (0.1 µm) contacts (RC ≈ 7.8 kΩ·µm). We also find that thermal annealing can relax the WS2 strain in long-contact devices, increasing RC to 8.5 kΩ·µm. These results reveal that thermo-mechanical phenomena can significantly influence 2D semiconductor-metal contacts, presenting opportunities to optimize device performance through nanofabrication and thermal budget.

Ambipolar Thickness-Dependent Thermoelectric Measurements of WSe2.

Thermoelectric materials can harvest electrical energy from temperature gradients, and could play a role as power supplies for sensors and other devices. Here, we characterize fundamental in-plane electrical and thermoelectric properties of layered WSe2 over a range of thicknesses, from 10 to 96 nm, between 300 and 400 K. The devices are electrostatically gated with an ion gel, enabling us to probe both electron and hole regimes over a large range of carrier densities. We extract the highest n- and p-type Seebeck coefficients for thin-film WSe2, -500 and 950 µV/K respectively, reported to date at room temperature. We also emphasize the importance of low substrate thermal conductivity on such lateral thermoelectric measurements, improving this platform for future studies on other nanomaterials.

Nanoscale temperature sensing of electronic devices with calibrated scanning thermal microscopy.

Heat dissipation threatens the performance and lifetime of many electronic devices. As the size of devices shrinks to the nanoscale, we require spatially and thermally resolved thermometry to observe their fine thermal features. Scanning thermal microscopy (SThM) has proven to be a versatile measurement tool for characterizing the temperature at the surface of devices with nanoscale resolution. SThM can obtain qualitative thermal maps of a device using an operating principle based on a heat exchange process between a thermo-sensitive probe and the sample surface. However, the quantification of these thermal features is one of the most challenging parts of this technique. Developing reliable calibration approaches for SThM is therefore an essential aspect to accurately determine the temperature at the surface of a sample or device. In this work, we calibrate a thermo-resistive SThM probe using heater-thermometer metal lines with different widths (50 nm to 750 nm), which mimic variable probe-sample thermal exchange processes. The sensitivity of the SThM probe when scanning the metal lines is also evaluated under different probe and line temperatures. Our results reveal that the calibration factor depends on the probe measuring conditions and on the size of the surface heating features. This approach is validated by mapping the temperature profile of a phase change electronic device. Our analysis provides new insights on how to convert the thermo-resistive SThM probe signal to the scanned device temperature more accurately.

Direct measurement of nanoscale filamentary hot spots in resistive memory devices.

Resistive random access memory (RRAM) is an important candidate for both digital, high-density data storage and for analog, neuromorphic computing. RRAM operation relies on the formation and rupture of nanoscale conductive filaments that carry enormous current densities and whose behavior lies at the heart of this technology. Here, we directly measure the temperature of these filaments in realistic RRAM with nanoscale resolution using scanning thermal microscopy. We use both conventional metal and ultrathin graphene electrodes, which enable the most thermally intimate measurement to date. Filaments can reach 1300°C during steady-state operation, but electrode temperatures seldom exceed 350°C because of thermal interface resistance. These results reveal the importance of thermal engineering for nanoscale RRAM toward ultradense data storage or neuromorphic operation.