Highly-packed self-assembled graphene oxide film-integrated resistive random-access memory on a silicon substrate for neuromorphic application.

Resistive random-access memories (RRAMs) based on metal-oxide thin films have been studied extensively for application as synaptic devices in neuromorphic systems. The use of graphene oxide (GO) as a switching layer offers an exciting alternative to other materials such as metal-oxides. We present a newly developed RRAM device fabricated by implementing highly-packed GO layers on a highly doped Si wafer to yield a gradual modulation of the memory as a function of the number of input pulses. By using flow-enabled self-assembly, highly uniform GO thin films can be formed on flat Si wafers in a rapid and simple process. The switching mechanism was explored through proposed scenarios reconstructing the density change of the sp2cluster in the GO layer, resulting in a gradual conductance modulation. We analyzed that the current in a low resistance state could flow by tunneling or hopping via clusters because the distance between the sp2clusters in closely-packed GO layers is short. Finally, through a pattern-recognition simulation with a Modified National Institute of Standards and Technology database, the feasibility of using close-packed GO layers as synapse devices was successfully demonstrated.

3-bit multilevel operation with accurate programming scheme in TiOx/Al2O3memristor crossbar array for quantized neuromorphic system.

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiOx/Al2O3-based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer.

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfOx-based metal-ferroelectric-insulator-semiconductor stack.

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al2O3layer between the SiO2insulator and the pure-HfOxFE improves the read disturbance (2Vc = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.

A novel physical unclonable function (PUF) using 16 × 16 pure-HfOxferroelectric tunnel junction array for security applications.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfOx)-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.

Analytically and empirically consistent characterization of the resistive switching mechanism in a Ag conducting-bridge random-access memory device through a pseudo-liquid interpretation approach.

A new physical analysis of the filament formation in a Ag conducting-bridge random-access memory (CBRAM) device in consideration of the existence of inter-atomic attractions caused by metal bonding is suggested. The movement of Ag atoms inside the switching layer is characterized hydrodynamically using the Young-Laplace equation during set and reset operations. Both meridional and azimuthal curvatures of the Ag filament protruding from the Ag electrode are accurately calculated to track down the exact shape of the Ag filament with change in the applied voltage. The second-order partial differential equation for the Ag filament geometry is derived from the equation of equilibrium between the electrostatic pressure and the Laplace one. The solution to the equation is numerically obtained, and furthermore, the abrupt set operation in the forming process, bipolar resistive-switching, and the threshold switching operation in the reset operations are successfully simulated in accordance with the numerical solutions. Also, it is demonstrated that the currents extracted from the suggested model show good agreement with the I-V characteristics measured from the fabricated Ag CBRAM device.

Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect.

In this research, we propose an Integrate-and-fire (I&F) Silicon-on-insulator (SOI) neuron circuit incorporating a Schmitt trigger as an action potential generating component. The Schmitt trigger is composed of four MOSFETs, and it presents hysteresis by controlling the threshold of one of the four MOSFET using back-gate effect. The presented circuit effectively handles input overflow by modulating output pulse duration, thus maintaining Rectified-linear-unit (ReLU) equivalence of I&F spiking neuron. The effect of overflow handling by output pulse modulation was further investigated by comparing the performance of single-layer spiking neural network (SNN) implemented using proposed circuit and conventional circuit. The ex-situ (offline) triained SNN implemented using the proposed circuit showed 1.8%p accuracy improvement in classifying 1000 MNIST handwritten digits compared to one implemented using conventional I&F neuron circuit due to elimination of quantization error.

Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a Thin-Film Transistor-Type NOR Flash Memory Array.

We present a two-layer fully connected neuromorphic system based on a thin-film transistor (TFT)-type NOR flash memory array with multiple postsynaptic (POST) neurons. Unsupervised online learning by spike-timing-dependent plasticity (STDP) on the binary MNIST handwritten datasets is implemented, and its recognition result is determined by measuring firing rate of POST neurons. Using a proposed learning scheme, we investigate the impact of the number of POST neurons in terms of recognition rate. In this neuromorphic system, lateral inhibition function and homeostatic property are exploited for competitive learning of multiple POST neurons. The simulation results demonstrate unsupervised online learning of the full black-and-white MNIST handwritten digits by STDP, which indicates the performance of pattern recognition and classification without preprocessing of input patterns.

Grayscale Image Recognition Using Spike-Rate-Based Online Learning and Threshold Adjustment of Neurons in a Thin-Film Transistor-Type NOR Flash Memory Array.

As a synaptic device, TFT-type NOR flash memory cell shows reasonable weight levels (50 levels for long-term potentiation (LTP) and 150 levels for long-term depression (LTD)) and large max/min ratio (═50) for synapse weight. Based on the measurement results of the synapse cell, supervised learning process is simulated using software MATLAB. A new pulse scheme is designed for mimicking spike-rate-dependent plasticity (SRDP) algorithm. Through learning and inferencing phase, our (784 × 100) network achieved 74.08% accuracy on the MNIST benchmark. A new method for adapting the threshold voltage of output neurons for firing is also proposed. This additional adjustment helps to eliminate the exclusive or dormant output neurons by setting the threshold voltage to an appropriate value proportional to the average weight of synapses connected to each neuron. As a result, accuracy increases to 82.54% in the (784 × 100) network and to 84.14% in the (784 × 200) network. Moreover, threshold adjustment helped the network to classify completely overlapped patterns in succession.

Nonvolatile Memory (NVM) Operation of Tunnel Field-Effect Transistor (TFET) Using Ferroelectric HfO2 Sidewall.

In this paper, we propose a new type of nonvolatile memory (NVM) device based on a tunnel field-effect transistor (TFETs) with Ferroelectric HfO2 sidewall. By simply utilizing the ferroelectricity of orthorhombic HfO2 and conventional sidewall spacer technique, TFET can operate as a NVM device. The polarized charges in the ferroelectric HfO2 spacer induced by program/erase pulse modulate the tunneling barrier between the source and channel; thus, change the threshold voltage (Vt) of TFET. The proposed NVM TFET has lower subthreshold swing (SS) and higher on/off ratio than conventional NVM TFETs while maintaining equivalent program/erase efficiency. Further-more, we also investigate the optimal HfO2 sidewall formation conditions to achieve higher NVM performances.

Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO2 layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

Transient Analysis of Tunnel Field-Effect Transistor with Raised Drain.

This paper investigates the electrical performance of a proposed tunnel field-effect transistor (TFET) via transient analysis. The proposed TFET has three features: a SiGe channel, a fin structure, and an elevated drain. As the SiGe channel and fin structure make a small tunnel resistance, the ONstate current can be increased. In addition, an elevated drain can suppress an ambipolar current (IAMB). The transient characteristics should be confirmed in terms of inverter switching for the high applicability of the proposed device to the logical circuit. The analysis is verified through technology computer-aided design (TCAD) simulations calibrated with rigorously fabricated devices. Based on the simulation results, we conclude that the proposed TFET shows better ON/OFF transient characteristics when compared to conventional TFETs and the small gate-to-drain capacitance (CGD) can improve the transient characteristics in TFET.

Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n-type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

An Online Learning Method Using Spike-Timing Dependent Plasticity for Neuromorphic Systems.

In this study, we proposed an online learning method using spike-timing dependent plasticity (STDP) whose operation is analogous to gradient descent, the most successful learning algorithm for nonspiking artificial neural networks (ANNs). With a model of a 4-terminal synaptic transistor we previously reported, a single-layer neural network implemented on the cross-point array was simulated by MATLAB to train binary MNIST samples with gradient descent algorithm. In addition, a proposed pulse scheme based on STDP was used to train the same network by applying teaching pulses having positive and negative timing differences with respect to input pulses to the back gate of the synaptic transistors. By comparing the extracted synaptic weight maps from both methods, therefore, the network trained by gradient descent was almost equally reproduced by the proposed method which was performed fully on hardware without computer calculation.

Tunnel Field Effect Transistor with Ferroelectric Gate Insulator.

Ferroelectric tunnel field effect transistor (Fe-TFET) having improved DC performance in comparison to the conventional TFET (c-TFET) is proposed and investigated through the technology computer-aided design (TCAD) simulation. By inserting ferroelectric material into the gate insulator of TFET, enhanced on-current (Ion) is obtained. It is attributed to the polarization characteristic of the ferroelectric materials which brings the capacitance boosting effect. Through the TCAD simulation, the characteristics of the ferroelectric material for the optimal performance conditions are also studied.

Analysis of Hot Carrier Injection According to Gate Length.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.

Analysis of Minority Carrier Lifetime Dependence on Dual Gate Feedback Field Effect Transistor.

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending on the channel condition or trap density, the lifetime of minority carrier can be degraded. Since the potential barrier lowering through the accumulated carriers is essential for positive feedback, the deterioration of lifetime can make a critical influence on the operation of device. Therefore, we verified the tendency of threshold voltage according to carrier lifetime and channel length. Through the comparison with p-n diode and FBFET, we drew the relation between lifetime and threshold voltage. As a result, it has been confirmed that the device with significantly deteriorated lifetime or the device with extremely long channel does not effectively generate feedback and loses its steep switching characteristics.

Partial Contact Etching and Gate Lowering on Tunneling Field Effect Transistor for Performance and Power Enhancement.

In this paper, it is shown that MOL capacitance reduction is one of the major performance boosting knobs for the tunneling field effect transistor (TFET) used for logic application. Low driving current is the weakness of TFET in terms of switching speed, however it can gain advantage fully from reducing MOL capacitance owing to negligible impact of MOL resistance degradation. We have proposed partial contact etching and gate height lowering to reduce MOL capacitance. As a result, 7.3% of delay improvement and 9.0% of reduced energy consumption is achieved with optimized MOL structure.

Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors.

Rather than the internal genome nucleic acids, the biomolecules on the surface of the influenza virus itself should be detected for a more exact and rapid point-of-care yes/no decision for influenza virus-induced infectious diseases. This work demonstrates the ultrasensitive electrical detection of the HA1 domain of hemagglutinin (HA), a representative viral surface protein of the influenza virus, using the top-down complementary metal oxide semiconductor (CMOS) processed silicon nanowire (SiNW) field-effect transistor (FET) configuration. Cytidine-5'-monophospho-N-acetylneuraminic acid (CMP-NANA) was employed as a probe that specifically binds both to the aldehyde self-aligned monolayer on the SiNWs and to HA1 simultaneously. CMP-NANA was serially combined with two kinds of linkers, namely 3-aminopropyltriethoxysilane and glutaraldehyde. The surface functionalization used was verified using the purification of glutathione S-transferase-tagged HA1, contact angle measurement, enzyme-linked immunosorbent assay test, and isoelectric focusing analysis. The proposed functionalized SiNW FET showed high sensitivities of the threshold voltage shift (ΔVT) ~51 mV/pH and the ΔVT = 112 mV (63 mV/decade) with an ultralow detectable range of 1 fM of target protein HA1.

Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate.

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.

An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET.

In this paper, we demonstrate the characteristics of the floating body effect of poly-silicon with grain boundary by SENTAURUS™ TCAD simulation. As drain voltage increases, impact ionization occurs at the drain-channel junction. And these holes created by impact ionization are deposited on the bottom of the body to change the threshold voltage. This feature, the kink effect, is also observed in fully depleted silicon on insulator because grain boundary of the poly-silicon serve as a storage to trap the holes. We simulate the transfer curve depending on the density and position of the grain boundary. The trap density of the grain boundary affects the device characteristics significantly. However similar properties appear except where the grain boundary is located on the drain side.