Flexible Solid-Electrolyte-Gated-Dielectric Carbon Nanotube Thin Film Transistors and Integrated Circuits with the Recorded Radiation Tolerance and Reparability.

Radiation-tolerance and repairable flexible transistors and integrated circuits (ICs) with low power consumption have become hot topics due to their wide applications in outer space, nuclear power plants, and X-ray imaging. Here, we designed and developed novel flexible semiconducting single-walled carbon nanotube (sc-SWCNT) thin-film transistors (TFTs) and ICs. Sc-SWCNT solid-electrolyte-gate dielectric (SEGD) TFTs showcase symmetric ambipolar characteristics with flat-band voltages (VFB) of ∼0 V, high ION/IOFF ratios (>105), and the recorded irradiation resistance (up to 22 Mrad). Moreover, flexible sc-SWCNT ICs, including CMOS-like inverters and NAND and NOR logic gates, have excellent operating characteristics with low power consumption (≤8.4 pW) and excellent irradiation resistance. Significantly, sc-SWCNT SEGD TFTs and ICs after radiation with a total irradiation dose (TID) ≥ 11 Mrad can be repaired after thermal heating at 100 °C. These outstanding characteristics are attributed to the designed device structures and key core materials including SEGD and sc-SWCNT.

(Bi,Sb)2 Se3 Alloy Thin Film for Short-Wavelength Infrared Photodetector and TFT Monolithic-Integrated Matrix Imaging.

Short-wavelength infrared photodetectors play a significant role in various fields such as autonomous driving, military security, and biological medicine. However, state-of-the-art short-wavelength infrared photodetectors, such as InGaAs, require high-temperature fabrication and heterogenous integration with complementary metal-oxide-semiconductor (CMOS) readout circuits (ROIC), resulting in a high cost and low imaging resolution. Herein, for the first time, a low-cost, high-performance, high-stable, and thin-film transistor (TFT) ROIC monolithic-integrated (Bi,Sb)2 Se3 alloy thin-film short-wavelength infrared photodetector is reported. The (Bi,Sb)2 Se3 alloy thin-film short-wavelength infrared photodetectors demonstrate a high external quantum efficiency (EQE) of 21.1% (light intensity of 0.76 µW cm-2 ) and a fast response time (3.24 µs). The highest EQE is about two magnitudes than that of the extrinsic photoconduction of Sb2 Se3 (0.051%). In addition, the unpackaged devices demonstrate high electric and thermal stability (almost no attenuation at 120 °C for 312 h), showing potential for in-vehicle applications that may experient such a high temperature. Finally, both the (Bi,Sb)2 Se3 alloy thin film and n-type CdSe buffer layer are directly deposited on the TFT ROIC (with a 64 × 64-pixel array) with a low-temperature process and the material identification and imaging applications are presented. This work is a significant breakthrough in ROIC monolithic-integrated short-wavelength infrared imaging chips.

Solution-processed bilayer InGaZnO/In2O3thin film transistors at low temperature by lightwave annealing.

At low temperatures about 230 °C, bilayer InGaZnO/In2O3thin film transistors (TFTs) were prepared by a solution process with lightwave annealing. The InGaZnO/In2O3bilayer TFTs with SiO2as dielectric layer show high electrical performances, such as a mobility of 7.63 cm2V-1s-1, a threshold voltage (Vth) of 3.8 V, and an on/off ratio higher than 107, which are superior to single-layer InGaZnO TFTs or In2O3TFTs. Moreover, bilayer InGaZnO/In2O3TFTs demonstrated a great bias stability enhancement due to the introduction of top InGaZnO film act as a passivation layer, which could prevent the interaction of ambient air with the bottom In2O3layer. By using high dielectric constant AlOxfilm, the InGaZnO/In2O3TFTs exhibit an improved mobility of 47.7 cm2V-1s-1. The excellent electrical performance of the solution-based InGaZnO/In2O3TFTs shows great application potential for low-cost flexible printed electronics.

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation.

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (µFE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a-IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (Vth), on-state current,µFEand gate bias stress stability of a-IGZO TFTs. A significant increase inµFEof over 8 fold, from 16 cm2Vs-1to 140 cm2Vs-1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Improved high voltage operation of amorphous In-Ga-Zn-O thin film transistor by carrier density enhancement.

We report on improved high voltage operation of amorphous-In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) by increasing carrier density and distributing the high bias field over the length of the device which utilizes an off-set drain structure. By decreasing the O2partial pressure during sputter deposition of IGZO, the channel carrier density of the high voltage a-IGZO TFT (HiVIT) was increased to ∼1018cm-3. Which reduced channel resistance and therefore the voltage drop in the ungated offset region during the on-state. To further decrease the electric field in the offset region, we applied Ta capping and subsequent oxidation to locally increase the oxygen vacancy levels in the offset region thereby increasing local carrier density. The reduction of the drain field in the offset region from 1.90 Vµm-1to 1.46 Vµm-1at 200 V drain voltage, significantly improved the operational stability of the device by reducing high field degradation. At an extreme drain voltage of 500 V, the device showed an off-state current of ∼10-11A and on-state current of ∼1.59 mA demonstrating that with further enhancements the HiVIT may be applicable to thin-film form, low leakage, high voltage control applications.

Facile synthesis ofß-Ga2O3based high-performance electronic devices via direct oxidation of solution-processed transition metal dichalcogenides.

Gallium oxide (Ga2O3) is a promising wide bandgap semiconductor that is viewed as a contender for the next generation of high-power electronics due to its high theoretical breakdown electric field and large Baliga's figure of merit. Here, we report a facile route of synthesizingß-Ga2O3via direct oxidation conversion using solution-processed two-dimensional (2D) GaS semiconducting nanomaterial. Higher order of crystallinity in x-ray diffraction patterns and full surface coverage formation in scanning electron microscopy images after annealing were achieved. A direct and wide bandgap of 5 eV was calculated, and the synthesizedß-Ga2O3was fabricated as thin film transistors (TFT). Theß-Ga2O3TFT fabricated exhibits remarkable electron mobility (1.28 cm2Vs-1) and a good current ratio (Ion/Ioff) of 2.06 × 105. To further boost the electrical performance and solve the structural imperfections resulting from the exfoliation process of the 2D nanoflakes, we also introduced and doped graphene inß-Ga2O3TFT devices, increasing the electrical device mobility by ∼8-fold and thereby promoting percolation pathways for the charge transport. We found that electron mobility and conductivity increase directly with the graphene doping concentration. From these results, it can be proved that theß-Ga2O3networks have excellent carrier transport properties. The facile and convenient synthesis method successfully developed in this paper makes an outstanding contribution to applying 2D oxide materials in different and emerging optoelectronic applications.

Plasma-enhanced atomic layer deposition of Sn-doped indium oxide semiconductor nano-films for thin-film transistors.

Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C- 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In-O/Sn-O in the ITO films, the relative percentage of In3+ions increases and that of Sn4+decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11thin-film transistors (TFTs) demonstrate high performance, includingµFEof 52.7 cm2V-1s-1, and a highION/IOFFof ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm-1and 85 °C, i.e. a minimalVthshift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs.

In2O3/ZnO heterojunction thin film transistor for high recognition accuracy neuromorphic computing and optoelectronic artificial synapses.

Solid electrolyte-gated transistors exhibit improved chemical stability and can fulfill the requirements of microelectronic packaging. Typically, metal oxide semiconductors are employed as channel materials. However, the extrinsic electron transport properties of these oxides, which are often prone to defects, pose limitations on the overall electrical performance. Achieving excellent repeatability and stability of transistors through the solution process remains a challenging task. In this study, we propose the utilization of a solution-based method to fabricate an In2O3/ZnO heterojunction structure, enabling the development of efficient multifunctional optoelectronic devices. The heterojunction's upper and lower interfaces induce energy band bending, resulting in the accumulation of a large number of electrons and a significant enhancement in transistor mobility. To mimic synaptic plasticity responses to electrical and optical stimuli, we utilize Li+-doped high-k ZrOxthin films as a solid electrolyte in the device. Notably, the heterojunction transistor-based convolutional neural network achieves a high accuracy rate of 93% in recognizing handwritten digits. Moreover, our research involves the simulation of a typical sensory neuron, specifically a nociceptor, within our synaptic transistor. This research offers a novel avenue for the advancement of cost-effective three-terminal thin-film transistors tailored for neuromorphic applications.

Ultrathin In2O3thin-film transistors deposited from trimethylindium and ozone.

Indium oxide (In2O3) is a promising channel material for thin-film transistors (TFTs). In this work, we develop an atomic layer deposition (ALD) process of using trimethylindium and ozone (O3) to deposit In2O3films and fabricate ultrathin In2O3TFTs. The In2O3TFTs with 4 nm channel thickness show generally good switching characteristics with a highIon/Ioffof 108, a high mobility (µFE) of 16.2cm2V-1s-1and a positive threshold voltage (Vth) of 0.48 V. Although the 4 nm In2O3TFTs exhibit short channel effect, it can be improved by adding an ALD Ga2O3capping layer to afford the bilayer In2O3/Ga2O3channel structure. The afforded In2O3/Ga2O3TFTs exhibit improved immunity to the short channel effect, with good TFT characteristics ofIon/Ioffof 107,µFEof 9.3cm2V-1s-1, and positiveVthof 2.23 V. Overall, the thermal budget of the entire process is only 400 °C, which is suitable for the display and CMOS back-end-of-line-compatible applications.

Thin-Film Transistor Digital Microfluidics Circuit Design with Capacitance-Based Droplet Sensing.

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets.

Strong Magnetic Field Annealing for Improved Phthalocyanine Organic Thin-Film Transistors.

Thin-film microstructure, morphology, and polymorphism can be controlled and optimized to improve the performance of carbon-based electronics. Thermal or solvent vapor annealing are common post-deposition processing techniques; however, it can be difficult to control or destructive to the active layer or substrates. Here, the use of a static, strong magnetic field (SMF) as a non-destructive process for the improvement of phthalocyanine (Pc) thin-film microstructure, increasing organic thin-film transistor (OTFTs) mobility by twofold, is demonstrated. Grazing incident wide-angle X-ray scattering (GIWAXS), X-ray diffraction (XRD), and atomic force microscopy (AFM) elucidate the effect of SMF on both para- and diamagnetic Pc thin-films when subjected to a magnetic field. A SMF is found to increase the concentration of oxygen-induced radical species within the Pc thin-film, lending a paramagnetic character to ordinarily diamagnetic metal-free Pc and resulting in magnetic field induced changes to its thin-film microstructures. In a nitrogen environment, without competing degradation effects of molecular oxygen, SMF processing is found to favorably improve charge transport characteristics and increase OTFT mobility. Thus, post-deposition thin-film annealing with a magnetic field is presented as an alternative and promising technique for future thin-film engineering applications.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In-Ga-Zn-O bilayer channel configuration.

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In-Ga-Zn-O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec-1), and high current drivability (13.6µAµm-1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm-1for 104s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Molecular layer modulation of two-dimensional organic ferroelectric transistors.

Ferroelectric transistors hold great potential in low consumption devices. Due to the high film quality and clean system, two dimensional organic semiconductors are widely employed to fabricate high performance organic electronic devices and explore the modulation mechanism of the molecular packing on device performance. Here, we combine the ferroelectric hafnium oxide HfZrOxand two-dimensional molecular crystal 2,9-didecyldinaphtho[2,3-b:2',3'-f]thieno[3,2b]thiophene (C10-DNTT) with controllable layers to study the molecular layer modulation of ferroelectric organic thin-film transistors (OTFTs). The contact resistance, driving current and transconductance are directly affected by the additional access resistance across the upper molecular layers at the source/drain contact region. Simultaneously, the capacitance of Schottky junction related to the molecular layer thickness could effectively adjust the gate potential acting on the organic channel, further controlling the devices' subthreshold swing and transconductance efficiency. This work would promote the development of low voltage and high performance OTFTs.

High-performance, semiconducting membrane composed of ultrathin, single-crystal organic semiconductors.

Thin film transistors (TFTs) are indispensable building blocks in any electronic device and play vital roles in switching, processing, and transmitting electronic information. TFT fabrication processes inherently require the sequential deposition of metal, semiconductor, and dielectric layers and so on, which makes it difficult to achieve reliable production of highly integrated devices. The integration issues are more apparent in organic TFTs (OTFTs), particularly for solution-processed organic semiconductors due to limits on which underlayers are compatible with the printing technologies. We demonstrate a ground-breaking methodology to integrate an active, semiconducting layer of OTFTs. In this method, a solution-processed, semiconducting membrane composed of few-molecular-layer-thick single-crystal organic semiconductors is exfoliated by water as a self-standing ultrathin membrane on the water surface and then transferred directly to any given underlayer. The ultrathin, semiconducting membrane preserves its original single crystallinity, resulting in excellent electronic properties with a high mobility up to 12 [Formula: see text] The ability to achieve transfer of wafer-scale single crystals with almost no deterioration of electrical properties means the present method is scalable. The demonstrations in this study show that the present transfer method can revolutionize printed electronics and constitute a key step forward in TFT fabrication processes.

Research Progress of Vertical Channel Thin Film Transistor Device.

Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel's length sub-1µm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs' active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

Bandlike Transport in FaPbBr3 Quantum Dot Phototransistor with High Hole Mobility and Ultrahigh Photodetectivity.

Halide perovskites have been widely explored for numerous optoelectronic applications among which phototransistors have appeared as one of the most promising light signal detectors. However, it is still a great challenge to endow halide perovskites with both mobility and high photosensitivity because of their high sensitivity to moisture in ambient atmosphere. Here, we explore an FAPbBr3 perovskite quantum dot (QD) phototransistor with bandlike charge transport and measure a dark hole mobility of 14.2 cm2 V-1 s-1 at ambient atmosphere. Attaining both high mobility and good optical figures of merit, a detectivity of ∼1016 Jones is achieved, which is a record for halide perovskite nanocrystals. Simple A-site salt (FABr) treatments offer a mechanism for connecting between perovskite QDs for better charge transfer in high-quality devices. All of these important properties are superior to most advanced inorganic semiconductor phototransistors, indicating a promising future in optoelectronic applications.

Stacking-Dependent Electrical Transport in a Colloidal CdSe Nanoplatelet Thin-Film Transistor.

Here, we report an exceptional feature of the one-dimensional threadlike assemblies of a four-monolayer colloidal CdSe nanoplatelet (NPL)-based thin-film transistor. A series of different lengths of threads (200-1200 nm) was used as an active n channel in thin-film transistors (TFTs) to understand the change in mobility with the length of the threads. The film with the longest threads shows the highest conductivity of ∼12 S/cm and electron mobility of ∼14.3 cm2 V-1 s-1 for an applied gate voltage of 2 V. The mobility trends with the length seem to be driven mostly by the lower defects in threads, where the loss of electron hopping is less. Furthermore, our results show the mobility trends in stacking-dependent CdSe NPL threads and provide a new insight into fabricating high-mobility TFTs with the use of colloidal CdSe NPLs.

A TSTDP memristive synapse based on a comprehensive mathematical model of memory-TFT threshold voltage shift.

New emerging nano-scale technologies like hydrogenated noncrystalline-silicon thin-film transistors (TFTs) and memristors, fabricated at low temperatures and over large areas, permit low-cost processing and 3D integration with CMOS cores. Here, we aim to propose a mathematical model which explains the memory-TFT threshold voltage shift due to the gate bias instability. Then, based on this mathematical approach, we propose a novel learning synapse composed of a voltage/flux driven memristor in parallel with a common-source memory-TFT with a memristive load. The proposed device realizes the triplet-based spike-timing-dependent plasticity rule (TSTDP) as a more realistic form of learning than the purely pair-based STDP (PSTDP). PSTDP is a synaptic learning rule which utilizes a constant-frequency pairing protocol to induce synaptic weight change and cannot explain the modification due to the frequency changes of spike pairs, and also the outcomes of triplet and quadruplet experiments. However, TSTDP improves the learning capabilities of the conventional PSTDP and reproduces the results of more electrophysiological experiments. In this paper, we apply various spike patterns like different-frequency and different-timing spike pairs, spike triplets, and quadruplets to the proposed device. Our simulations confirm a close match with the experimental data sets of real biological synapses.

High-sensitivity hybrid PbSe/ITZO thin film-based phototransistor detecting from 2100 to 2500 nm near-infrared illumination.

We report that high absorption PbSe colloidal quantum dots (QDs) having a peak absorbance beyond 2100 nm were synthesized and incorporated into InSnZnO (ITZO) channel layer-based thin film transistors (TFTs). It was intended that PbSe QDs with proportionally less photocurrent modulation can be remedied by semiconducting and low off-current ITZO-based TFT configuration. Multiple deposition scheme of PbSe QDs on ITZO metal oxide thin film gave rise to nearly linear increase of film thickness with acceptably uniform and smooth surface (less than 10 nm). Hybrid PbSe/ITZO thin film-based phototransistor exhibited the best performance of near infrared (NIR) detection in terms of response time, sensitivity and detectivity as high as 0.38 s, 3.91 and 4.55 × 107Jones at room temperature, respectively. This is indebted mainly from the effective diffusion of photogenerated carrier from the PbSe surface to ITZO channel layer as well as from the conduction band alignment between them. Therefore, we believe that our hybrid PbSe/ITZO material platform can be widely used to be in favour of incorporation of solution-processed colloidal light absorbing material into the high-performance metal oxide thin film transistor configuration.

Low-temperature n-type doping of insulating ultrathin amorphous indium oxide using H plasma-assisted annealing.

Low-temperature process compatibility is a key factor in successfully constructing additional functional circuits on top of pre-existing circuitry without corrupting characteristics thereof, a technique that typically requires die-to-die (wafer-to-wafer) stacking and interconnecting. And against thermal annealing, which is mandatory and is possible only globally for activating amorphous oxide semiconductors, the selective control of electrical characteristics of the oxide thin-films for integrated circuit applications is challenging. Here, a low-temperature process that enables n-type doping of the designed region of insulating In2O3thin-film is demonstrated. A short hydrogen plasma treatment followed by low-temperature annealing is used to increase interstitial and substitutional hydrogen associated bond states creating shallow donor levels in the insulating In2O3surface to transform the thin-film into an n-type semiconductor. As a result, an In2O3thin-film transistor with a high on/off current ratio (>108), a field-effect mobility of 3.8 cm2V-1s-1, and a threshold voltage of ∼3.0 V has been developed. Compared to performing just thermal annealing, the H-plasma assisted annealing process resulted in an n-type In2O3thin-film transistor showing similar characteristics, while the processing time was reduced by ∼1/3 and the plasma-untreated area still remained insulating. With further development, the hydrogen plasma doping process may make possible a monolithic planar process technology for amorphous oxide semiconductors.