RESUMEN
Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (Vbl) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive Vbl countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive Vbl scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.
RESUMEN
This study investigates the effects of hydrogen post-treatment on 3D NAND flash memory. Hydrogen post-treatment annealing (PTA) is suggested to passivate the defects in the tunneling oxide/poly-Si interface and inside the poly-Si channel. However, excess hydrogen PTA can release hydrogen atoms from the passivated defects, which may degrade device performance. Therefore, it is important to determine the appropriate PTA condition for optimization of the device performance. Three different conditions for hydrogen PTA, namely Reference, H, and H++, are applied to observe the effects on device performance. The activation energy (Ea) of the device parameters was extracted according to the hydrogen PTA condition to analyze the effects. The extractedEais about 74 meV for Reference, 53 meV for H, and 58 meV for H++conditions, with the best performance observed at the H condition. Optimal hydrogen PTA shows the best on-current (51% higher than Reference) and stable short-term retention (66% suppressedΔVTthan Reference) in 9X stacked 3D NAND flash memory.
RESUMEN
The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.
RESUMEN
Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).
RESUMEN
Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (-30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells' degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.
RESUMEN
We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance-voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.