First demonstration of robust tri-gateß-Ga2O3nano-membrane field-effect transistors.

Nano-membrane tri-gateß-gallium oxide (ß-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface betweenß-Ga2O3and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al2O3) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec-1, high drain current (IDS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (I-V) characteristics measured at temperatures up to 400 °C.

Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics.

Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)-textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.

Highly stable 2D material (2DM) field-effect transistors (FETs) with wafer-scale multidyad encapsulation.

Field-effect transistors (FETs) composed of 2D materials (2DMs) such as transition-metal dichalcogenide (TMD) materials show unstable electrical characteristics in ambient air due to the high sensitivity of 2DMs to water adsorbates. In this work, in order to demonstrate the long-term retention of electrical characteristics of a TMD FET, a multidyad encapsulation method was applied to a MoS2 FET and thereby its durability was warranted for one month. It was well known that the multidyad encapsulation method was effective to mitigate high sensitivity to ambient air in light-emitting diodes (LEDs) composed of organic materials. However, there was no attempt to check the feasibility of such a multidyad encapsulation method for 2DM FETs. It is timely to investigate the water vapor transmission ratio (WVTR) required for long-term stability of 2DM FETs. The 2DM FETs were fabricated with MoS2 flakes by both an exfoliation method, that is desirable to attain high quality film, and a chemical vapor deposition (CVD) method, that is applicable to fabrication for a large-sized substrate. In order to eliminate other unwanted variables, the MoS2 FETs composed of exfoliated flakes were primarily investigated to assure the effectiveness of the encapsulation method. The encapsulation method uses multiple dyads comprised of a polymer layer by spin coating and an Al2O3 layer deposited by atomic layer deposition (ALD). The proposed method shows wafer-scale uniformity, high transparency, and protective barrier properties against adsorbates (WVTR of 8 × 10-6 g m-2 day-1) over one month.

Simulational investigation of self-aligned bilayer linear grating enabling highly enhanced responsivity of MWIR InAs/GaSb type-II superlattice (T2SL) photodetector.

Linear gratings polarizers provide remarkable potential to customize the polarization properties and tailor device functionality via dimensional tuning of configurations. Here, we extensively investigate the polarization properties of single- and double-layer linear grating, mainly focusing on self-aligned bilayer linear grating (SABLG), serving as a wire grid polarizer in the mid-wavelength infrared (MWIR) region. Computational analyses revealed the polarization properties of SABLG, highlighting enhancement in TM transmission and reduction in TE transmission compared to single-layer linear gratings (SLG) due to optical cavity effects. As a result, the extinction ratio is enhanced by approximately 2724-fold in wavelength 3-6 µm. Furthermore, integrating the specially designed SABLG with an MWIR InAs/GaSb Type-II Superlattice (T2SL) photodetector yields a significantly enhanced spectral responsivity. The TM-spectral responsivity of SABLG is enhanced by around twofold than the bare device. The simulation methodology and analytical analysis presented herein provide a versatile route for designing optimized polarimetric structures integrated into infrared imaging devices, offering superior capabilities to resolve linear polarization signatures.

Influence of Radiation-Induced Displacement Defect in 1.2 kV SiC Metal-Oxide-Semiconductor Field-Effect Transistors.

The effect of displacement defect on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) due to radiation is investigated using technology computer-aided design (TCAD) simulation. The position, energy level, and concentration of the displacement defect are considered as variables. The transfer characteristics, breakdown voltage, and energy loss of a double-pulse switching test circuit are analyzed. Compared with the shallow defect energy level, the deepest defect energy level with EC - 1.55 eV exhibits considerable degradation. The on-current decreases by 54% and on-resistance increases by 293% due to the displacement defect generated at the parasitic junction field-effect transistor (JFET) region next to the P-well. Due to the existence of a defect in the drift region, the breakdown voltage increased up to 21 V. In the double-pulse switching test, the impact of displacement defect on the power loss of SiC MOSFETs is negligible.

On-State Current Degradation Owing to Displacement Defect by Terrestrial Cosmic Rays in Nanosheet FET.

Silicon displacement defects are caused by various effects. For instance, epitaxial crystalline silicon growth and ion implantation often result in defects induced by the fabrication process, whereas displacement damage is induced by terrestrial cosmic radiation. Clustered displacement damage reportedly reduces the on-state current (Ion) in ordinary MOSFETs. In the case of an extremely scaled device such as a nanosheet field-effect transistor (NS-FET), the impact of displacement defect size was analyzed on the basis of the NS dimensions related to the device characteristics. In this study, we investigated the effect of displacement defects on NS-FETs using technology computer-aided design; the simulation model included quantum transport effects. The geometrical conditions, temperatures, trap concentrations, and scattering models were considered as the variables for on-state current reduction.

Highly enhanced ferroelectricity in HfO2-based ferroelectric thin film by light ion bombardment.

Continuous advancement in nonvolatile and morphotropic beyond-Moore electronic devices requires integration of ferroelectric and semiconductor materials. The emergence of hafnium oxide (HfO2)-based ferroelectrics that are compatible with atomic-layer deposition has opened interesting and promising avenues of research. However, the origins of ferroelectricity and pathways to controlling it in HfO2 are still mysterious. We demonstrate that local helium (He) implantation can activate ferroelectricity in these materials. The possible competing mechanisms, including He ion-induced molar volume changes, vacancy redistribution, vacancy generation, and activation of vacancy mobility, are analyzed. These findings both reveal the origins of ferroelectricity in this system and open pathways for nanoengineered binary ferroelectrics.

Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure.

For the first time, a novel germanium (Ge) bi-stable resistor (biristor) with a vertical pillar structure was implemented on a bulk substrate. The basic structure of the Ge pillar-typed biristor is a p-n-p bipolar junction transistor (BJT) with an open base (floating), which is equivalent to a gateless p-channel metal oxide semiconductor field-effect transistor (MOSFET). In the pillar formation, we adopted an amorphous carbon layer to protect the Ge surface from both physical and chemical damage by subsequent processes. A hysteric current-voltage (I-V) characteristic, which results in a sustainable binary state, i.e., high current and low current at the same voltage, can be utilized for a memory device. A lower operating voltage with high current was achieved, compared to a Si biristor, due to the low energy bandgap of pure Ge.

Nanoscale FET-Based Transduction toward Sensitive Extended-Gate Biosensors.

Owing to their simple and low-cost architecture, extended-gate biosensors based on the combination of a disposable sensing part and a reusable transducer have been widely utilized for the label-free electrical detection of chemical and biological species. Previous studies have demonstrated that sensitive and selective detection of ions and biomolecules can be achieved by controlled modification of the sensing part with an ion-selective membrane and receptors of interest. However, no systematic studies have been performed on the impact of the transducer on sensing performance. In this paper, we introduce the concept of a nanoscale field-effect transistor (FET) as a reusable and sensitive transducer for extended-gate biosensors. The capacitive effect from the external sensing part can degrade the sensing performance, but the nanoscale FET can reduce this effect. The nanoscale FET with a gate-all-around (GAA) structure exhibits a higher pH sensitivity than a commercially available FET, which is widely used in conventional extended-gate biosensors. A sensitivity reduction is observed for the commercial FET, whereas the pH sensitivity is insensitive to the area of the sensing region in the nanoscale FET, thus allowing the scaling of the detection area. Our analysis based on a capacitive model suggests that the high pH sensitivity in the compact sensing area originates from the small input capacitance of the nanoscale FET transducer. Moreover, a decrease in the nanowire width of the GAA FET leads to an improvement in the pH sensitivity. The extended-gate approach with the nanoscale FET-based transduction can pave the way for a highly sensitive analysis of chemical and biological species with a small sample volume.

Solar-Blind UV Photodetector Based on Atomic Layer-Deposited Cu2O and Nanomembrane ß-Ga2O3 pn Oxide Heterojunction.

Herein, we present a solar-blind ultraviolet photodetector realized using atomic layer-deposited p-type cuprous oxide (Cu2O) underneath a mechanically exfoliated n-type ß-gallium oxide (ß-Ga2O3) nanomembrane. The atomic layer deposition process of the Cu2O film applies bis(N,N'-di-secbutylacetamidinato)dicopper(I) [Cu(5Bu-Me-amd)]2 as a novel Cu precursor and water vapor as an oxidant. The exfoliated ß-Ga2O3 nanomembrane was transferred to the top of the Cu2O layer surface to realize a unique oxide pn heterojunction, which is not easy to realize by conventional oxide epitaxy techniques. The current-voltage (I-V) characteristics of the fabricated pn heterojunction diode show the typical rectifying behavior. The fabricated Cu2O/ß-Ga2O3 photodetector achieves sensitive detection of current at the picoampere scale in the reverse mode. This work provides a new approach to integrate all oxide heterojunctions using membrane transfer and bonding techniques, which goes beyond the limitation of conventional heteroepitaxy.

Localized Electrothermal Annealing with Nanowatt Power for a Silicon Nanowire Field-Effect Transistor.

This work investigates localized electrothermal annealing (ETA) with extremely low power consumption. The proposed method utilizes, for the first time, tunneling-current-induced Joule heat in a p-i-n diode, consisting of p-type, intrinsic, and n-type semiconductors. The consumed power used for dopant control is the lowest value ever reported. A metal-oxide-semiconductor field-effect transistor (MOSFET) composed of a p-i-n silicon nanowire, which is a substructure of a tunneling FET (TFET), was fabricated and utilized as a test platform to examine the annealing behaviors. A more than 2-fold increase in the on-state (ION) current was achieved using the ETA. Simulations are conducted to investigate the location of the hot spot and how its change in heat profile activates the dopants.

On-Chip Curing by Microwave for Long Term Usage of Electronic Devices in Harsh Environments.

Microwave-induced thermal curing is demonstrated to improve the reliability and to prolong the lifetime of chips containing nanoscale electron devices. A film containing graphite powder with high microwave absorbing efficiency was fabricated at low cost. The film is flexible, bendable, foldable, and attachable to a chip. A commercial off-the-shelf chip and a representative 3-dimensional (3D) metal-oxide-semiconductor field-effect transistor (MOSFET), known as FinFET, were utilized to verify the curing behaviors of the microwave-induced heat treatment. The heat effectively cured not only total ionizing dose (TID) damage from the external environment, but also internal electrical stress such as hot-carrier injection (HCI), which are representative sources of damages in MOSFET insulators. Then, the characteristics of the pre- and post-curing electron devices are investigated using electrical measurements and numerical simulations.

Nano-electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments.

A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of the NEM-switch-based PUF is its use of stiction. Stiction is one of the chronic problems associated with micro- and nano-electromechanical system (MEMS/NEMS) devices; however, here, it was utilized to intentionally implement a PUF for hardware-based security. The stiction is caused by capillary and van der Waals forces, producing strong adhesion, which can be utilized to design a highly robust and stable PUF. The probability that stiction will occur on either of two gates in the NEM switch is the same, and consequently, the occurrence of the stiction is random and unique, which is critical to its PUF performance. This uniqueness was evaluated by measuring the interchip Hamming distance (interchip HD), which characterizes how different responses are made when the same challenge is applied. Uniformity was also evaluated by the proportion of "1" or "0" in the response bit-string. The reliability of the proposed PUF device was assessed by stress tests under harsh environments such as high temperature, high dose radiation, and microwaves.

Foldable and Disposable Memory on Paper.

Foldable organic memory on cellulose nanofibril paper with bendable and rollable characteristics is demonstrated by employing initiated chemical vapor deposition (iCVD) for polymerization of the resistive switching layer and inkjet printing of the electrode, where iCVD based on all-dry and room temperature process is very suitable for paper electronics. This memory exhibits a low operation voltage of 1.5 V enabling battery operation compared to previous reports and wide memory window. The memory performance is maintained after folding tests, showing high endurance. Furthermore, the quick and complete disposable nature demonstrated here is attractive for security applications. This work provides an effective platform for green, foldable and disposable electronics based on low cost and versatile materials.

Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application.

We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106 seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10 seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric.

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm(2) V(-1) sec(-)1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 10(4)), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs).

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.

Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.

The memory for the Internet of Things (IoT) requires versatile characteristics such as flexibility, wearability, and stability in outdoor environments. Resistive random access memory (RRAM) to harness a simple structure and organic material with good flexibility can be an attractive candidate for IoT memory. However, its solution-oriented process and unclear switching mechanism are critical problems. Here we demonstrate iCVD polymer-intercalated RRAM (i-RRAM). i-RRAM exhibits robust flexibility and versatile wearability on any substrate. Stable operation of i-RRAM, even in water, is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package. Moreover, the direct observation of a carbon filament is also reported for the first time using transmission electron microscopy, which puts an end to the controversy surrounding the switching mechanism. Therefore, reproducibility is feasible through comprehensive modeling. Furthermore, a carbon filament is superior to a metal filament in terms of the design window and selection of the electrode material. These results suggest an alternative to solve the critical issues of organic RRAM and an optimized memory type suitable for the IoT era.