First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates.

A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node and beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) of SiGe selective to Si, formation of SiGe/Si core/shell NS/NW structure, building of nitride dummy gate, and replacement of the dummy gate. This fabrication method is complementary metal oxide semiconductor (CMOS)-compatible, simple, and reproducible, and NWs with a diameter of 17 nm and NSs with a thickness of 20 nm were obtained. Excellent control of short-channel-effects was presented. The device performance was also investigated and discussed. The proposed integration scheme has great potential for applications in chip manufacturing, especially with vertical channel devices.

Giant Anisotropy of Spin Relaxation and Spin-Valley Mixing in a Silicon Quantum Dot.

In silicon quantum dots (QDs), at a certain magnetic field commonly referred to as the "hot spot," the electron spin relaxation rate (T_{1}^{-1}) can be drastically enhanced due to strong spin-valley mixing. Here, we experimentally find that with a valley splitting of 78.2±1.6 µeV, this hot spot in spin relaxation can be suppressed by more than 2 orders of magnitude when the in-plane magnetic field is oriented at an optimal angle, about 9° from the [100] sample plane. This directional anisotropy exhibits a sinusoidal modulation with a 180° periodicity. We explain the magnitude and phase of this modulation using a model that accounts for both spin-valley mixing and intravalley spin-orbit mixing. The generality of this phenomenon is also confirmed by tuning the electric field and the valley splitting up to 268.5±0.7 µeV.

Amorphous oxide semiconductor for monolithic 3D DRAM: an enabler or passer-by?

Whether amorphous oxide semiconductor (AOS) is an enabler or pass-by for monolithic 3D DRAM is discussed, with current challenges and future directions proposed in this perspective.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

Gate-defined quantum point contacts in a germanium quantum well.

We report an experimental study of quantum point contacts defined in a high-quality strained germanium quantum well with layered electric gates. At a zero magnetic field, we observed quantized conductance plateaus in units of 2e2/h. Bias-spectroscopy measurements reveal that the energy spacing between successive one-dimensional subbands ranges from 1.5 to 5 meV as a consequence of the small effective mass of the holes and the narrow gate constrictions. At finite magnetic fields perpendicular to the device plane, the edges of the conductance plateaus get split due to the Zeeman effect and Landé g factors were estimated to be ∼6.6 for the holes in the germanium quantum well. We demonstrate that all quantum point contacts in the same device have comparable performances, indicating a reliable and reproducible device fabrication process. Thus, our work lays a foundation for investigating multiple forefronts of physics in germanium-based quantum devices that require quantum point contacts as building blocks.

Effective electrical manipulation of a topological antiferromagnet by orbital torques.

The electrical control of the non-trivial topology in Weyl antiferromagnets is of great interest for the development of next-generation spintronic devices. Recent studies suggest that the spin Hall effect can switch the topological antiferromagnetic order. However, the switching efficiency remains relatively low. Here, we demonstrate the effective manipulation of antiferromagnetic order in the Weyl semimetal Mn3Sn using orbital torques originating from either metal Mn or oxide CuOx. Although Mn3Sn can convert orbital current to spin current on its own, we find that inserting a heavy metal layer, such as Pt, of appropriate thickness can effectively reduce the critical switching current density by one order of magnitude. In addition, we show that the memristor-like switching behaviour of Mn3Sn can mimic the potentiation and depression processes of a synapse with high linearity-which may be beneficial for constructing accurate artificial neural networks. Our work paves a way for manipulating the topological antiferromagnetic order and may inspire more high-performance antiferromagnetic functional devices.

Highly Energy-Efficient Spin Current Generation in SrIrO3 by Manipulating the Octahedral Rotation.

Materials with strong spin-orbit coupling (SOC) have been continuously attracting intensive attention due to their promising application in energy-efficient, high-density, and nonvolatile spintronic devices. Particularly, transition-metal perovskite oxides with strong SOC have been demonstrated to exhibit efficient charge-spin interconversion. In this study, we systematically investigated the impact of epitaxial strain on the spin-orbit torque (SOT) efficiency in the SrIrO3(SIO)/Ni81Fe19(Py) bilayer. The results reveal that the SOT efficiency is strongly related to the octahedral rotation around the in-plane axes of the single-crystal SIO. By modulating the epitaxial strain using different substrates, the SOT efficiency can be remarkably improved from 0.15 to 1.45. This 10-fold enhancement of SOT efficiency suggests that modulating the epitaxial strain is an efficient approach to control the SOT efficiency in complex oxide-based heterostructures. Our work may have the potential to advance the application of complex oxides in energy-efficient spintronic devices.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks.

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control". A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an "exposed top" structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique.

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 µs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (-2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 µA/µm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process.

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions.

SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiH2Cl2, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated. The interface quality was characterized by transmission electron microscopy/atomic force microscopy/high-resolution X-ray diffraction methods. It was observed that limiting the migration of Ge atoms in the interface was critical for optimizing a sharp interface, and the addition of DCS was found to decrease the interface transition thickness. The change of the interfacial transition layer is not significant in the short treatment time of HCl. When the processing time of HCl is increased, the internal interface is optimized to a certain extent but the corresponding film thickness is also reduced. This study provides technical support for the acquisition of an abrupt interface and will have a very favorable influence on the performance improvement of miniaturized devices in the future.

Undoped Strained Ge Quantum Well with Ultrahigh Mobility of Two Million.

We develop a method to fabricate an undoped Ge quantum well (QW) under a 32 nm relaxed Si0.2Ge0.8 shallow barrier. The bottom barrier contains Si0.2Ge0.8 (650 °C) and Si0.1Ge0.9 (800 °C) such that variation of Ge content forms a sharp interface that can suppress the threading dislocation density (TDD) penetrating into the undoped Ge quantum well. The SiGe barrier introduces enough in-plane parallel strain (ε∥ strain -0.41%) in the Ge quantum well. The heterostructure field-effect transistors with a shallow buried channel obtain an ultrahigh two-dimensional hole gas (2DHG) mobility over 2 × 106 cm2/(V s) and a very low percolation density of (5.689 ± 0.062) × 1010 cm-2. The fractional indication is also observed at high density and high magnetic fields. This strained germanium as a noise mitigation material provides a platform for integration of quantum computation with a long coherence time and fast all-electrical manipulation.

Special Issue: Silicon Nanodevices.

In recent years, nanodevices have attracted a large amount of attention due to their low power consumption and fast operation in electronics and photonics, as well as their high sensitivity in sensor applications [...].

A Voltage-Modulated Nanostrip Spin-Wave Filter and Spin Logic Device Thereof.

A nanostrip magnonic-crystal waveguide with spatially periodic width modulation can serve as a gigahertz-range spin-wave filter. Compared with the regular constant-width nanostrip, the periodic width modulation creates forbidden bands (band gaps) at the Brillouin zone boundaries due to the spin-wave reflection by the periodic potential owing to the long-range dipolar interactions. Previous works have shown that there is a critical challenge in tuning the band structures of the magnonic-crystal waveguide once it is fabricated. In this work, using micromagnetic simulations, we show that voltage-controlled magnetic anisotropy can effectively tune the band structures of a ferromagnetic-dielectric heterostructural magnonic-crystal waveguide. A uniformly applied voltage of 0.1 V/nm can lead to a significant frequency shift of ~9 GHz. A spin-wave transistor prototype employing such a kind of spin-wave filter is proposed to realize various logical operations. Our results could be significant for future magnonic computing applications.

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.