Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor.

Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal-oxide-semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less TFETs (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10-6A and 16.6 mV dec-1, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs.

Design of n+-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector.

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (I on /I off ) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a [Formula: see text] bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Etch characteristics of magnetic tunnel junction materials using H2/NH3 reactive ion beam.

Magnetic tunneling junction (MTJ) materials such as CoFeB, Co, Pt, MgO, and the hard mask material such as W and TiN were etched with a reactive ion beam etching (RIBE) system using H2/NH3. By using gas mixtures of H2 and NH3, especially with the H2/NH3( 2:1) ratio, higher etch rates of MTJ related materials and higher etch selectivities over mask materials (>30) could be observed compared to those etching using pure H2( no etching) and NH3. In addition, no significant chemical and physical damages were observed on etched magnetic materials surfaces and, for CoPt and MTJ nanoscale patterns etched by the H2/NH3( 2:1) ion beam, highly anisotropic etch profiles >83° with no sidewall redeposition could be observed. The higher etch rates of magnetic materials such as CoFeB by the H2/NH3( 2:1) ion beam compared to those by H2 ion beam or NH3 ion beam are believed to be related to the formation of volatile metal hydrides (MH, M = Co, Fe, etc) through the reduction of M-NHx( x = 1 ∼ 3) formed in the CoFeB surface by the exposure to NH3 ion beam. It is believed that the H2/NH3 RIBE is a suitable technique in the etching of MTJ materials for the next generation nanoscale spin transfer torque magnetic random access memory (STT-MRAM) devices.

Dislocation sink annihilating threading dislocations in strain-relaxed Si1-x Ge x layer.

We proposed a dislocation sink technology for achieving Si1-x Ge x multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si1-x Ge x channel. A generation of a dislocation sink via H+ implantations in a strain-relaxed Si0.7Ge0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si0.7Ge0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [SiI or GeI + V Si or V Ge â†’ Si1-x Ge x ] annihilation process, where SiI, GeI, V Si, and V Ge are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H+ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 1015 atoms cm-2 and 800 °C.

Effect of coupling ability between a synthetic antiferromagnetic layer and pinned layer on a bridging layer of Ta, Ti, and Pt in perpendicular-magnetic tunnel junctions.

By fabricating CoFeB/MgO/CoFeB-based perpendicular-magnetic tunnel junction (p-MTJ) spin-valves stacked with a [Co/Pd] n -SyAF layer based on a TiN bottom electrode on a 12 inch Si wafer (001) substrate, we investigated how the bridging layers of Ta, Ti, and Pt and their thickness variation affected the tunneling magneto-resistance (TMR) ratio of Co2Fe6B2 pinned-layer behavior in magnetic-tunnel-junctions. TMR ratios for Ta, Ti, and Pt bridging layers were observed to be 64.1, 70.2, and 29.5%, respectively. It was confirmed by high resolution transmission electron microscopy (HR-TEM) that this difference resulted from CoFeB/MgO/CoFeB MTJ layers with Ta and Ti bridging layers being textured well with a bcc (100) structure, indicating that Ta and Ti bridging layers bridged SyAF fcc (111) and MTJ bcc (100). On the other hand, the MTJ layer with Pt bridging layer was incorrectly textured, indicating that a Pt bridging layer is unsuitable to bridge SyAF fcc (111) and MTJ bcc (100) due to Pt being diffused into the CoFeB pinned-layer. In addition, perpendicular magnetic anisotropy (PMA) behavior of the CoFeB pinned-layer was found to depend strongly on a bridging layer thickness; higher TMRs of Ta and Ti were observed at the optimal bridging layers' thickness, which enable the realization of PMAs of the pinned-layer and ferro-coupling of the pinned-layer with the lower-SyAF layer. Among the three bridging materials (Ta, Ti, and Pt), we observed that Ti showed the highest TMR ratio and widest thickness range for a high TMR ratio, indicating that a higher TMR ratio is needed to obtain the best deposition process margin.

Dependency of tunneling magnetoresistance ratio on Pt seed-layer thickness for double MgO perpendicular magnetic tunneling junction spin-valves with a top Co2Fe6B2 free layer ex-situ annealed at 400 °C.

For the double MgO based perpendicular magnetic tunneling junction (p-MTJ) spin-valves with a top Co2Fe6B2 free layer ex situ annealed at 400 °C, the tunneling-magnetoresistance ratio (TMR) strongly depended on the platinum (Pt) seed layer thickness (t Pt): it peaked (∼134%) at a specific t Pt (3.3 nm). The TMR ratio was initially and slightly increased from 113%-134% by the enhancement of the magnetic moment of the Co2Fe6B2 pinned layer when t Pt increased from 2.0-3.3 nm, and then rapidly decreased from 134%-38.6% by the degrading face-centered-cubic crystallinity of the MgO tunneling barrier when t Pt increased from 3.3-14.3 nm.

Co2Fe6B2/MgO-based perpendicular spin-transfer-torque magnetic-tunnel-junction spin-valve without [Co/Pt] n lower synthetic-antiferromagnetic layer.

We design a Co2Fe6B2/MgO-based p-MTJ spin-valve without a [Co/Pt] n lower synthetic-antiferromagnetic (SyAF) layer to greatly reduce the 12-inch wafer fabrication cost of the p-MTJ spin-valve. This spin-valve achieve a tunneling magnetoresistance (TMR) of 158% and an exchange field (H ex) of 1.4 kOe at an ex situ annealing temperature of >350 °C, which ensures writing error immunity. In particular, the TMR ratio strongly depends on the body-center-cubic capping-layer nanoscale thickness (t bcc), i.e., the TMR ratio peaks at t bcc = 0.6 nm.

Influence of face-centered-cubic texturing of Co2Fe6B2 pinned layer on tunneling magnetoresistance ratio decrease in Co2Fe6B2/MgO-based p-MTJ spin valves stacked with a [Co/Pd](n)-SyAF layer.

The TMR ratio of Co2Fe6B2/MgO-based p-MTJ spin valves stacked with a [Co/Pd]n-SyAF layer decreased rapidly when the ex situ magnetic annealing temperature (Tex) was increased from 275 to 325 °C, and this decrease was associated with degradation of the Co2Fe6B2 pinned layer rather than the Co2Fe6B2 free layer. At a Tex above 325 °C the amorphous Co2Fe6B2 pinned layer was transformed into a face-centered-cubic (fcc) crystalline layer textured from [Co/Pd]n-SyAF, abruptly reducing the Δ1 coherence tunneling of perpendicular-spin-torque electrons between the (100) MgO tunneling barrier and the fcc Co2Fe6B2 pinned layer.

Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode.

Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 10(5) s with a memory margin of 9.2 × 10(5), program/erase endurance cycles of >10(2) with a memory margin of 8.4 × 10(5), and bending-fatigue-free cycles of ∼1 × 10(3) with a memory margin (I(on)/I(off)) of 3.3 × 10(5).

The energy-down-shift effect of Cd(0.5)Zn(0.5)S-ZnS core-shell quantum dots on power-conversion-efficiency enhancement in silicon solar cells.

We found that Cd0.5Zn0.5S-ZnS core (4.2 nm in diameter)-shell (1.2 nm in thickness) quantum dots (QDs) demonstrated a typical energy-down-shift (2.76-4.96 → 2.81 eV), which absorb ultra-violet (UV) light (250-450 nm in wavelength) and emit blue visible light (∼442 nm in wavelength). They showed the quantum yield of ∼80% and their coating on the SiNX film textured p-type silicon solar-cells enhanced the external-quantum-efficiency (EQE) of ∼30% at 300-450 nm in wavelength, thereby enhancing the short-circuit-current-density (JSC) of ∼2.23 mA cm(-2) and the power-conversion-efficiency (PCE) of ∼1.08% (relatively ∼6.04% increase compared with the reference without QDs for p-type silicon solar-cells). In particular, the PCE peaked at a specific coating thickness of the Cd0.5Zn0.5S-ZnS core-shell QD layer; i.e., the 1.08% PCE enhancement at the 8.8 nm thick QD layer.

Potassium Iodide Doping for Vacancy Substitution and Dangling Bond Repair in InP Core-Shell Quantum Dots.

This work highlights the novel approach of incorporating potassium iodide (KI) doping during the synthesis of In0.53P0.47 core quantum dots (QDs) to significantly reduce the concentration of vacancies (i.e., In vacancies; VIn-) within the bulk of the core QD and inhibit the formation of InPOx at the core QD-Zn0.6Se0.4 shell interfaces. The photoluminescence quantum yield (PLQY) of ~97% and full width at half maximum (FWHM) of ~40 nm were achieved for In0.53P0.47/Zn0.6Se0.4/Zn0.6Se0.1S0.3/Zn0.5S0.5 core/multi-shell QDs emitting red light, which is essential for a quantum-dot organic light-emitting diode (QD-OLED) without red, green, and blue crosstalk. KI doping eliminated VIn- in the core QD bulk by forming K+-VIn- substitutes and effectively inhibited the formation of InPO4(H2O)2 at the core QD-Zn0.6Se0.4 shell interface through the passivation of phosphorus (P)-dangling bonds by P-I bonds. The elimination of vacancies in the core QD bulk was evidenced by the decreased relative intensity of non-radiative unpaired electrons, measured by electron spin resonance (ESR). Additionally, the inhibition of InPO4(H2O)2 formation at the core QD and shell interface was confirmed by the absence of the {210} X-ray diffraction (XRD) peak intensity for the core/multi-shell QDs. By finely tuning the doping concentration, the optimal level was achieved, ensuring maximum K-VIn- substitution, minimal K+ and I- interstitials, and maximum P-dangling bond passivation. This resulted in the smallest core QD diameter distribution and maximized optical properties. Consequently, the maximum PLQY (~97%) and minimum FWHM (~40 nm) were observed at 3% KI doping. Furthermore, the color gamut of a QD-OLED display using R-, G-, and B-QD functional color filters (i.e., ~131.1%@NTSC and ~98.2@Rec.2020) provided a nearly perfect color representation, where red-light-emitting KI-doped QDs were applied.

Hybrid Organic-Si C-MOSFET Image Sensor Designed with Blue-, Green-, and Red-Sensitive Organic Photodiodes on Si C-MOSFET-Based Photo Signal Sensor Circuit.

The resolution of Si complementary metal-oxide-semiconductor field-effect transistor (C-MOSFET) image sensors (CISs) has been intensively enhanced to follow the technological revolution of smartphones, AI devices, autonomous cars, robots, and drones, approaching the physical and material limits of a resolution increase in conventional Si CISs because of the low quantum efficiency (i.e., ~40%) and aperture ratio (i.e., ~60%). As a novel solution, a hybrid organic-Si image sensor was developed by implementing B, G, and R organic photodiodes on four n-MOSFETs for photocurrent sensing. Photosensitive organic donor and acceptor materials were designed with cost-effective small molecules, i.e., the B, G, and R donor and acceptor small molecules were Coumarin6 and C_60, DMQA and MePTC, and ZnPc and TiOPc, respectively. The output voltage sensing margins (i.e., photocurrent signal difference) of the hybrid organic-Si B, G, and R image sensor pixels presented results 17, 11, and 37% higher than those of conventional Si CISs. In addition, the hybrid organic-Si B, G, and R image sensor pixels could achieve an ideal aperture ratio (i.e., ~100%) compared with a Si CIS pixel using the backside illumination process (i.e., ~60%). Moreover, they may display a lower fabrication cost than image sensors because of the simple image sensor structure (i.e., hybrid organic-Si photodiode with four n-MOSFETs).

Fumed Silica-Based Ultra-High-Purity Synthetic Quartz Powder via Sol-Gel Process for Advanced Semiconductor Process beyond Design Rule of 3 nm.

Fumed silica-based ultra-high-purity synthetic quartz powder was developed via the sol-gel process to apply to quartz wares and quartz crucibles for use in advanced semiconductor processes. The process conditions of preparing potassium silicate solution, gelation, and cleaning were optimized, i.e., the relative ratio of fumed silica (10 wt%) to KOH (4 wt%) for potassium silicate solution, gelation time 3 h, and cleaning for 1 h with 5 wt% HCl solution. It was observed that the gelation time strongly affected the size distribution of the quartz powder; i.e., a longer gelation time led to a larger size (d50) of the synthesized quartz powder: 157 µm for 2 h and 331 µm for 5 h. In particular, it was found that the morphology of the as-synthesized quartz powder greatly depended on the pulverizing process; i.e., the shape of quartz powder was shown to be rod-shaped for the without-gel-pulverizing process and granular-shaped with the process. We expect that the fumed silica-based ultra-high-purity quartz powder with an impurity level of 74.1 ppb synthesized via the sol-gel process is applicable as a raw material for quartz wares and crucibles for advanced semiconductor processes beyond the design rule of 3 nm.

Polymer photovoltaic cell embedded with p-type single walled carbon nanotubes fabricated by spray process.

In the current study, we fabricated polymer (poly(3-hexylthiophene-2,5-diyl) (P3HT) and [6,6]-phenyl-C(61) butyric-acid methyl-ester (PCBM) blend) photovoltaic (PV) cells embedded with p-type single walled carbon nanotubes (SWCNTs) with tangled hair morphology. The power conversion efficiency (PCE) rapidly increased with SWCNT concentration of up to 6.83% coverage, and then decreased and saturated with increasing SWCNT concentration; i.e., the PCE peaks at 5.379%. This tendency is mainly associated with hole transport efficiency toward the transparent electrode (indium-tin-oxide (ITO)) via SWCNTs, directly determining the series resistance and shunt resistance of the polymer PV cells embedded with SWCNTs: the PV cell is increasing shunt resistance and decreasing series resistance.

Silicon Wafer CMP Slurry Using a Hydrolysis Reaction Accelerator with an Amine Functional Group Remarkably Enhances Polishing Rate.

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very high Si polishing rate (500 nm/min) by accelerating the degree of the hydrolysis reaction (i.e., Si-O-H) on the polished Si wafer surface during CMP. Unlike conventional hydrolysis reaction accelerators (i.e., sodium hydroxide and potassium hydroxide), a novel hydrolysis reaction accelerator with amine functional groups (i.e., 552.8 nm/min for ethylenediamine) surprisingly presented an Si wafer polishing rate >3 times higher than that of conventional hydrolysis reaction accelerators (177.1 nm/min for sodium hydroxide). This remarkable enhancement of the Si wafer polishing rate for ethylenediamine was principally the result of (i) the increased hydrolysis reaction, (ii) the enhanced degree of adsorption of the CMP slurry on the polished Si wafer surface during CMP, and (iii) the decreased electrostatic repulsive force between colloidal silica abrasives and the Si wafer surface. A higher ethylenediamine concentration in the Si wafer CMP slurry led to a higher extent of hydrolysis reaction and degree of adsorption for the slurry and a lower electrostatic repulsive force; thus, a higher ethylenediamine concentration resulted in a higher Si wafer polishing rate. With the aim of achieving further improvements to the Si wafer polishing rates using Si wafer CMP slurry including ethylenediamine, the Si wafer polishing rate increased remarkably and root-squarely with the increasing ethylenediamine concentration.

Surface Transformation of Spin-on-Carbon Film via Forming Carbon Iron Complex for Remarkably Enhanced Polishing Rate.

To scale down semiconductor devices to a size less than the design rule of 10 nm, lithography using a carbon polymer hard-mask was applied, e.g., spin-on-carbon (SOC) film. Spin coating of the SOC film produces a high surface topography induced by pattern density, requiring chemical-mechanical planarization (CMP) for removing such high surface topography. To achieve a relatively high polishing rate of the SOC film surface, the CMP principally requires a carbon-carbon (C-C) bond breakage on the SOC film surface. A new design of CMP slurry evidently accomplished C-C bond breakage via transformation from a hard surface with strong C-C covalent bonds into a soft surface with a metal carbon complex (i.e., C=Fe=C bonds) during CMP, resulting in a remarkable increase in the rate of the SOC film surface transformation with an increase in ferric catalyst concentration. However, this surface transformation on the SOC film surface resulted in a noticeable increase in the absorption degree (i.e., hydrophilicity) of the SOC film CMP slurry on the polished SOC film surface during CMP. The polishing rate of the SOC film surface decreased notably with increasing ferric catalyst concentration. Therefore, the maximum polishing rate of the SOC film surface (i.e., 272.3 nm/min) could be achieved with a specific ferric catalyst concentration (0.05 wt%), which was around seven times higher than the me-chanical-only CMP.

Polymer link breakage of polyimide-film-surface using hydrolysis reaction accelerator for enhancing chemical-mechanical-planarization polishing-rate.

In this study, the chemical decomposition of a polyimide-film (i.e., a PI-film)-surface into a soft-film-surface containing negatively charged pyromellitic dianhydride (PMDA) and neutral 4,4'-oxydianiline (ODA) was successfully performed. The chemical decomposition was conducted by designing the slurry containing 350 nm colloidal silica abrasive and small molecules with amine functional groups (i.e., ethylenediamine: EDA) for chemical-mechanical planarization (CMP). This chemical decomposition was performed through two types of hydrolysis reactions, that is, a hydrolysis reaction between OH- ions or R-NH3+ (i.e., EDA with a positively charged amine groups) and oxygen atoms covalently bonded with pyromellitimide on the PI-film-surface. In particular, the degree of slurry adsorption of the PI-film-surface was determined by the EDA concentration in the slurry because of the presence of R-NH3+, that is, a higher EDA concentration resulted in a higher degree of slurry adsorption. In addition, during CMP, the chemical decomposition degree of the PI-film-surface was principally determined by the EDA concentration; that is, the degree of chemical composition was increased noticeably and linearly with the EDA concentration. Thus, the polishing-rate of the PI-film-surface increased notably with the EDA concentration in the CMP slurry.

Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3 Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array.

The learning and inference efficiencies of an artificial neural network represented by a cross-point synaptic memristor array can be achieved using a selector, with high selectivity (Ion /Ioff ) and sufficient death region, stacked vertically on a synaptic memristor. This can prevent a sneak current in the memristor array. A selector with multiple jar-shaped conductive Cu filaments in the resistive switching layer is precisely fabricated by designing the Cu ion concentration depth profile of the CuGeSe layer as a filament source, TiN diffusion barrier layer, and Ge3 Se7 switching layer. The selector performs super-linear-threshold-switching with a selectivity of > 107 , death region of -0.70-0.65 V, holding time of 300 ns, switching speed of 25 ns, and endurance cycle of > 106 . In addition, the mechanism of switching is proven by the formation of conductive Cu filaments between the CuGeSe and Ge3 Se7 layers under a positive bias on the top Pt electrode and an automatic rupture of the filaments after the holding time. Particularly, a spiking deep neural network using the designed one-selector-one-memory cross-point array improves the Modified National Institute of Standards and Technology classification accuracy by ≈3.8% by eliminating the sneak current in the cross-point array during the inference process.

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator.

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.

Super fine cerium hydroxide abrasives for SiO2 film chemical mechanical planarization performing scratch free.

Face-centered-cubic crystallized super-fine (~ 2 nm in size) wet-ceria-abrasives are synthesized using a novel wet precipitation process that comprises a Ce4+ precursor, C3H4N2 catalyst, and NaOH titrant for a synthesized termination process at temperature of at temperature of 25 °C. This process overcomes the limitations of chemical-mechanical-planarization (CMP)-induced scratches from conventional dry ceria abrasives with irregular surfaces or wet ceria abrasives with crystalline facets in nanoscale semiconductor devices. The chemical composition of super-fine wet ceria abrasives depends on the synthesis termination pH, that is, Ce(OH)4 abrasives at a pH of 4.0-5.0 and a mixture of CeO2 and Ce(OH)4 abrasives at a pH of 5.5-6.5. The Ce(OH)4 abrasives demonstrate better abrasive stability in the SiO2-film CMP slurry than the CeO2 abrasives and produce a minimum abrasive zeta potential (~ 12 mV) and a minimum secondary abrasive size (~ 130 nm) at the synthesis termination pH of 5.0. Additionally, the abrasive stability of the SiO2-film CMP slurry that includes super-fine wet ceria abrasives is notably sensitive to the CMP slurry pH; the best abrasive stability (i.e., a minimum secondary abrasive size of ~ 130 nm) is observed at a specific pH (6.0). As a result, a maximum SiO2-film polishing rate (~ 524 nm/min) is achieved at pH 6.0, and the surface is free of stick-and-slip type scratches.