A machine learning approach to model the impact of line edge roughness on gate-all-around nanowire FETs while reducing the carbon footprint.

The performance and reliability of semiconductor devices scaled down to the sub-nanometer regime are being seriously affected by process-induced variability. To properly assess the impact of the different sources of fluctuations, such as line edge roughness (LER), statistical analyses involving large samples of device configurations are needed. The computational cost of such studies can be very high if 3D advanced simulation tools (TCAD) that include quantum effects are used. In this work, we present a machine learning approach to model the impact of LER on two gate-all-around nanowire FETs that is able to dramatically decrease the computational effort, thus reducing the carbon footprint of the study, while obtaining great accuracy. Finally, we demonstrate that transfer learning techniques can decrease the computing cost even further, being the carbon footprint of the study just 0.18 g of CO2 (whereas a single device TCAD study can produce up to 2.6 kg of CO2), while obtaining coefficient of determination values larger than 0.985 when using only a 10% of the input samples.

Special Issue: Nanowire Field-Effect Transistor (FET).

This Special Issue looks at recent developments in the research field of Nanowire Field-Effect Transistors (NW-FETs), covering different aspects of technology, physics, and modelling of these nanoscale devices. In this summary, we present seven outstanding articles on NW-FETs by providing a brief overview of the articles' content.

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs.

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 µA/µm, and an on-current (I ON) of 1770 µA/µm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55 . 5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

Atomistic mesh generation for the simulation of nanoscale metal-oxide-semiconductor field-effect transistors.

We present a methodology for the finite-element discretization of nanoscaled semiconductor devices with atomic resolution. The meshing strategy is based on the use of patterns to decompose the unit cell of the underlying crystallographic structures producing unstructured tetrahedral meshes. The unit cells of the bulk semiconductors and, more importantly, of the interfaces between the substrate and the gate dielectric have been extracted from classical molecular dynamics and density functional theory simulations. A Monte Carlo approach has been then used to place the dopants in nodes of the crystal, replacing silicon atoms. The thus created "atomistic" meshes are used to simulate an ensemble of microscopically different double-gate Si metal-oxide-semiconductor field-effect transistors and the transition region at the Si/SiO_{2} interface. In addition, a methodology to approximate amorphous dielectrics is also presented.

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness.

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando's and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height ([Formula: see text]). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando's model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with [Formula: see text] channel orientation are affected more by the IRS than those with the [Formula: see text] crystal orientation. Finally, Λ and [Formula: see text] are shown to affect the device performance similarly. A change in values by 30% (Λ) or [Formula: see text] ([Formula: see text]) results in an increase (decrease) of up to [Formula: see text] in the drive current.