Selective area epitaxy of GaAs: the unintuitive role of feature size and pitch.

Selective area epitaxy (SAE) provides the path for scalable fabrication of semiconductor nanostructures in a device-compatible configuration. In the current paradigm, SAE is understood as localized epitaxy, and is modelled by combining planar and self-assembled nanowire growth mechanisms. Here we use GaAs SAE as a model system to provide a different perspective. First, we provide evidence of the significant impact of the annealing stage in the calculation of the growth rates. Then, by elucidating the effect of geometrical constraints on the growth of the semiconductor crystal, we demonstrate the role of adatom desorption and resorption beyond the direct-impingement and diffusion-limited regime. Our theoretical model explains the effect of these constraints on the growth, and in particular why the SAE growth rate is highly sensitive to the pattern geometry. Finally, the disagreement of the model at the largest pitch points to non-negligible multiple adatom recycling between patterned features. Overall, our findings point out the importance of considering adatom diffusion, adsorption and desorption dynamics in designing the SAE pattern to create pre-determined nanoscale structures across a wafer. These results are fundamental for the SAE process to become viable in the semiconductor industry.

Single-Crystalline γ-Ga2S3 Nanotubes via Epitaxial Conversion of GaAs Nanowires.

The chemical transformation of nanowire templates into nanotubes is a promising avenue toward hollow one-dimensional (1D) nanostructures. To date, high-quality single crystalline tubes of nonlayered inorganic crystals have been obtained by solid-state reactions in diffusion couples of nanowires with deposited thin film shells, but this approach presents issues in achieving single-phase tubes with a desired stoichiometry. Chemical transformations with reactants supplied from the gas- or vapor-phase can avoid these complications, allowing single-phase nanotubes to be obtained through self-termination of the reaction once the sacrificial template has been consumed. Here, we demonstrate the realization of this scenario with the transformation of zincblende GaAs nanowires into single-crystalline cubic γ-Ga2S3 nanotubes by reaction with sulfur vapor. The conversion proceeds via the formation of epitaxial GaAs-Ga2S3 core-shell structures, vacancy injection and aggregation into Kirkendall voids, elastic relaxation of the detached Ga2S3 shell, and finally complete incorporation of Ga in a crystalline chalcogenide tube. Absorption and luminescence spectroscopy on individual nanotubes show optoelectronic properties, notably a ∼3.1 eV bandgap and intense band-edge and near band-edge emission consistent with high-quality single crystals, along with transitions between gap-states due to the inherent cation-vacancy defect structure of Ga2S3. Our work establishes the transformation of nanowires via vapor-phase reactions as a viable approach for forming single-crystalline hollow 1D nanostructures with promising properties.

Telecom-Wavelength Bottom-up Nanobeam Lasers on Silicon-on-Insulator.

Semiconductor nanowire lasers are considered promising ultracompact and energy-efficient light sources in the field of nanophotonics. Although the integration of nanowire lasers onto silicon photonic platforms is an innovative path toward chip-scale optical communications and photonic integrated circuits, operating nanowire lasers at telecom-wavelengths remains challenging. Here, we report on InGaAs nanowire array lasers on a silicon-on-insulator platform operating up to 1440 nm at room temperature. Bottom-up photonic crystal nanobeam cavities are formed by growing nanowires as ordered arrays using selective-area epitaxy, and single-mode lasing by optical pumping is demonstrated. We also show that arrays of nanobeam lasers with individually tunable wavelengths can be integrated on a single chip by the simple adjustment of the lithographically defined growth pattern. These results exemplify a practical approach toward nanowire lasers for silicon photonics.

Unveiling the complex phonon nature and phonon cascades in 1L to 5L WSe2 using multiwavelength excitation Raman scattering.

Tungsten diselenide (WSe2) is a 2D semiconducting material, promising for novel optoelectronic and phononic applications. WSe2 has complex lattice dynamics and phonon structure. Numerous discrepancies in the literature exist regarding the interpretation and identification of phonon modes. This work presents a complete investigation of the vibrational properties of 1L to 5L flakes and bulk WSe2 using multi-wavelength Raman spectroscopy. We especially highlight measurements using 785 nm excitation, which have not been performed before. These allow us to solve inconsistences in the literature in terms of defect-activated non-Γ point single phonon modes and Breit-Wigner-Fano type resonance. We identify 35 Raman peaks per flake thickness, which we attribute to either one-phonon or multi-phonon modes, including two-phonon scattering due to a van Hove singularity (vHs). The measurements are in excellent agreement with the theoretical predictions. Using photoluminescence measurements, we identify photon-exciton coupling leading to resonant Raman scattering, suggesting wavelength laser excitations best suited for further investigations of specific WSe2 flake thicknesses. Finally, we report the observation of phonon-cascades for all WSe2 flake thicknesses, indicating strong phonon-electron interactions during early carrier relaxation processes in WSe2. This research provides a solid foundation and reference for future investigations of the vibrational properties of WSe2, paving the way for further development of this material towards applications.

Nanoscale Mapping of Light Emission in Nanospade-Based InGaAs Quantum Wells Integrated on Si(100): Implications for Dual Light-Emitting Devices.

III-V semiconductors outperform Si in many optoelectronics applications due to their high carrier mobility, efficient light emission and absorption processes, and the possibility to engineer their band gap through alloying. However, complementing Si technology with III-V semiconductors by integration on Si(100) remains a challenge still today. Vertical nanospades (NSPDs) are quasi-bi-crystal III-V nanostructures that grow on Si(100). Here, we showcase the potential of these structures in optoelectronics application by demonstrating InGaAs heterostructures on GaAs NSPDs that exhibit bright emission in the near-infrared region. Using cathodoluminescence hyperspectral imaging, we are able to study light emission properties at a few nanometers of spatial resolution, well below the optical diffraction limit. We observe a symmetric spatial luminescence splitting throughout the NSPD. We correlate this characteristic to the structure's crystal nature, thus opening new perspectives for dual wavelength light-emitting diode structures. This work paves the path for integrating optically active III-V structures on the Si(100) platform.

GaAs nanowires on Si nanopillars: towards large scale, phase-engineered arrays.

Large-scale patterning for vapor-liquid-solid growth of III-V nanowires is a challenge given the required feature size for patterning (45 to 60 nm holes). In fact, arrays are traditionally manufactured using electron-beam lithography,for which processing times increase greatly when expanding the exposure area. In order to bring nanowire arrays one step closer to the wafer-scale we take a different approach and replace patterned nanoscale holes with Si nanopillar arrays. The method is compatible with photolithography methods such as phase-shift lithography or deep ultraviolet (DUV) stepper lithography. We provide clear evidence on the advantage of using nanopillars as opposed to nanoscale holes both for the control on the growth mechanisms and for the scalability. We identify the engineering of the contact angle as the key parameter to optimize the yield. In particular, we demonstrate how nanopillar oxidation is key to stabilize the Ga catalyst droplet and engineer the contact angle. We demonstrate how the position of the triple phase line at the SiO2/Si as opposed to the SiO2/vacuum interface is central for a successful growth. We compare our experiments with simulations performed in surface evolver™ and observe a strong correlation. Large-scale arrays using phase-shift lithography result in a maximum local vertical yield of 67% and a global chip-scale yield of 40%. We believe that, through a greater control over key processing steps typically achieved in a semiconductor fab it is possible to push this yield to 90+% and open perspectives for deterministic nanowire phase engineering at the wafer-scale.

III-V Integration on Si(100): Vertical Nanospades.

III-V integration on Si(100) is a challenge: controlled vertical vapor liquid solid nanowire growth on this platform has not been reported so far. Here we demonstrate an atypical GaAs vertical nanostructure on Si(100), coined nanospade, obtained by a nonconventional droplet catalyst pinning. The Ga droplet is positioned at the tip of an ultrathin Si pillar with a radial oxide envelope. The pinning at the Si/oxide interface allows the engineering of the contact angle beyond the Young-Dupré equation and the growth of vertical nanospades. Nanospades exhibit a virtually defect-free bicrystalline nature. Our growth model explains how a pentagonal twinning event at the initial stages of growth provokes the formation of the nanospade. The optical properties of the nanospades are consistent with the high crystal purity, making these structures viable for use in integration of optoelectronics on the Si(100) platform.