Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

Strain-driven mound formation of substrate under epitaxial nanoparticles.

We observe the growth of crystalline SiC nanoparticles on Si(001) at 900 °C using in situ electron microscopy. Following nucleation and growth of the SiC, there is a massive migration of Si, forming a crystalline Si mound underneath each nanoparticle that lifts it 4-5 nm above the initial growth surface. The volume of the Si mounds is roughly five to seven times the volume of the SiC nanoparticles. We propose that relaxation of strain drives the mound formation. This new mechanism for relieving interfacial strain, which involves a dramatic restructuring of the substrate, is in striking contrast to the familiar scenario in which only the deposited material restructures to relieve strain.

Vertical III-V nanowire device integration on Si(100).

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode.

Epitaxial growth of SrTiO3 on silicon by molecular beam epitaxy has opened up the route to the integration of functional complex oxides on a silicon platform. Chief among them is ferroelectric functionality using perovskite oxides such as BaTiO3. However, it has remained a challenge to achieve ferroelectricity in epitaxial BaTiO3 films with a polarization pointing perpendicular to the silicon substrate without a conducting bottom electrode. Here, we demonstrate ferroelectricity in such stacks. Synchrotron X-ray diffraction and high-resolution scanning transmission electron microscopy reveal the presence of crystalline domains with the long axis of the tetragonal structure oriented perpendicular to the substrate. Using piezoforce microscopy, polar domains can be written and read and are reversibly switched with a phase change of 180°. Open, saturated hysteresis loops are recorded. Thus, ferroelectric switching of 8- to 40-nm-thick BaTiO3 films in metal-ferroelectric-semiconductor structures is realized, and field-effect devices using this epitaxial oxide stack can be envisaged.

Epitaxial graphene nanoribbon array fabrication using BCP-assisted nanolithography.

A process for fabricating dense graphene nanoribbon arrays using self-assembled patterns of block copolymers on graphene grown epitaxially on SiC on the wafer scale has been developed. Etching masks comprising long and straight nanoribbon array structures with linewidths as narrow as 10 nm were fabricated, and the patterns were transferred to graphene. Our process combines both top-down and self-assembly steps to fabricate long graphene nanoribbon arrays with low defect counts. These are the narrowest nanoribbon arrays of epitaxial graphene on SiC fabricated to date.