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Reliable fabrication of lateral interfaces between conducting and semiconducting 2D materials is considered a major technological advancement for the next generation of highly packed all-2D electronic circuitry. This study employs seed-free consecutive chemical vapor deposition processes to synthesize high-quality lateral MoS2 -graphene heterostructures and comprehensively investigated their electronic properties through a combination of various experimental techniques and theoretical modeling. These results show that the MoS2 -graphene devices exhibit an order of magnitude higher mobility and lower noise metrics compared to conventional MoS2 -metal devices as a result of energy band rearrangement and smaller Schottky barrier height at the contacts. These findings suggest that MoS2 -graphene in-plane heterostructures are promising materials for the scale-up of all-2D circuitry with superlative electrical performance.
RESUMEN
Heterostructures based on atomic monolayers are emerging as leading materials for future energy efficient and multifunctional electronics. Due to the single atom thickness of monolayers, their properties are strongly affected by interactions with the external environment. We develop a model for interface thermal conductance (ITC) in an atomic monolayer van der Waals bonded to a disordered substrate. Graphene on SiO2 is initially used in our model and contrasted against available experimental data; the model is then applied to monolayer molybdenum disulfide (MoS2) on SiO2 substrate. Our findings show the dominant carrier of heat in both graphene and MoS2 in the cross-plane direction is the flexural (ZA) phonon mode, owing to the large overlap between graphene ZA and substrate vibrational density of states. The rate of phonon transfer across the interface depends quadratically on the substrate coupling constant K a , but this interaction also causes a lifting of the lowest flexural phonon modes. As a result, ITC depends roughly linearly on the strength of the coupling between a monolayer and its substrate. We conclude that, in both graphene and MoS2 on SiO2, substrate adhesion plays a strong role in determining ITC, requiring further study of substrate coupling in TMDCs.
RESUMEN
Few-layer (FL) transition-metal dichalcogenides have drawn attention for nanoelectronics applications due to their improved mobility, owing to the partial screening of charged impurities at the oxide interface. However, under realistic operating conditions, dissipation leads to self-heating, which is detrimental to electronic and thermal properties. We fabricated a series of FL-WSe2 devices and measured their I-V characteristics, while their temperatures were quantified by Raman thermometry and simulated from first principles. Our tightly integrated electrothermal study shows that Joule heating leads to a significant layer-dependent temperature rise, which affects mobility and alters the flow of current through the stack. This causes the temperatures in the top layers to increase dramatically, degrading their mobility and causing the current to reroute to the bottom of the FL stack where thermal conductance is higher. We discover that this current rerouting phenomenon improves heat removal because the current flows through layers closer to the substrate, limiting the severity of self-heating and its impact on carrier mobility. We also observe significant lateral heat removal via the contacts because of longer thermal healing length in the top layers and explore the optimum number of layers to maximize mobility in FL devices. Our study will impact future device designs and lead to further improvements in thermal management in van der Waals (vdW)-based devices.
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The ongoing shrinkage in the size of two-dimensional (2D) electronic circuitry results in high power densities during device operation, which could cause a significant temperature rise within 2D channels. One challenge in Raman thermometry of 2D materials is that the commonly used high-frequency modes do not precisely represent the temperature rise in some 2D materials because of peak broadening and intensity weakening at elevated temperatures. In this work, we show that a low-frequency E2g2 shear mode can be used to accurately extract temperature and measure thermal boundary conductance (TBC) in back-gated tungsten diselenide (WSe2) field-effect transistors, whereas the high-frequency peaks (E2g1 and A1g) fail to provide reliable thermal information. Our calculations indicate that the broadening of high-frequency Raman-active modes is primarily driven by anharmonic decay into pairs of longitudinal acoustic phonons, resulting in a weak coupling with out-of-plane flexural acoustic phonons that are responsible for the heat transfer to the substrate. We found that the TBC at the interface of WSe2 and Si/SiO2 substrate is â¼16 MW/m2 K, depends on the number of WSe2 layers, and peaks for 3-4 layer stacks. Furthermore, the TBC to the substrate is the highest from the layers closest to it, with each additional layer adding thermal resistance. We conclude that the location where heat dissipated in a multilayer stack is as important to device reliability as the total TBC.
RESUMEN
Van der Waals interactions in 2D materials have enabled the realization of nanoelectronics with high-density vertical integration. Yet, poor energy transport through such 2D-2D and 2D-3D interfaces can limit a device's performance due to overheating. One long-standing question in the field is how different encapsulating layers (e.g., contact metals or gate oxides) contribute to the thermal transport at the interface of 2D materials with their 3D substrates. Here, a novel self-heating/self-sensing electrical thermometry platform is developed based on atomically thin, metallic Ti3 C2 MXene sheets, which enables experimental investigation of the thermal transport at a Ti3 C2 /SiO2 interface, with and without an aluminum oxide (AlOx ) encapsulating layer. It is found that at room temperature, the thermal boundary conductance (TBC) increases from 10.8 to 19.5 MW m-2 K-1 upon AlOx encapsulation. Boltzmann transport modeling reveals that the TBC can be understood as a series combination of an external resistance between the MXene and the substrate, due to the coupling of low-frequency flexural acoustic (ZA) phonons to substrate modes, and an internal resistance between ZA and in-plane phonon modes. It is revealed that internal resistance is a bottle-neck to heat removal and that encapsulation speeds up the heat transfer into low-frequency ZA modes and reduces their depopulation, thus increasing the effective TBC.
RESUMEN
We study the impact of grain boundaries (GB) and misorientation angles between grains on electronic transport in 2-dimensional materials. Here we have developed a numerical model based on the first-principles electronic bandstructure calculations in conjunction with a method which computes electron transmission coefficients from simultaneous conservation of energy and momentum at the interface to essentially evaluate GB/interface resistance in a Landauer formalism. We find that the resistance across graphene GBs vary over a wide range depending on misorientation angles and type of GBs, starting from 53 Ω µm for low-mismatch angles in twin (symmetric) GBs to about 1020 Ω µm for 21° mismatch in tilt (asymmetric) GBs. On the other hand, misorientation angles have weak influence on the resistance across MoS2 GBs, ranging from about 130 Ω µm for low mismatch angles to about 6000 Ω µm for 21°. The interface resistance across graphene-MoS2 heterojunctions also exhibits a strong dependence on misorientation angles with resistance values ranging from about 100 Ω µm for low-mismatch angles in Class-I (symmetric) interfaces to 1015 Ω µm for 14° mismatch in Class-II (asymmetric) interfaces. Overall, symmetric homo/heterojunctions exhibit a weak dependence on misorientation angles, while in MoS2 both symmetric and asymmetric GBs show a gradual dependence on mismatch angles.