Reliable fabrication of sub-10 nm silicon nanowires by optical lithography.

The reliable and controllable fabrication of silicon nanowires is achieved, using mature CMOS technology processes. This will enable a low-cost route to integrating novel nanostructures with CMOS logic. The challenge of process repeatability has been overcome by careful study of material properties for processes such as etching and oxidation. By controlling anisotropic wet etching conditions, selection of nitride mask layer properties and sidewall oxidation, a robust process was achieved to realize silicon nanowires with sub 10 nm features. Surface roughness of nanowires was improved by a suitable oxidation step. The influence of process conditions on the shape of the nanowire was studied using TCAD simulation.

Experimental observation of negative capacitance in ferroelectrics at room temperature.

Effective negative capacitance has been postulated in ferroelectrics because there is a hysteresis in plots of polarization-electric field. Compelling experimental evidence of effective negative capacitance is presented here at room temperature in engineered devices, where it is stabilized by the presence of a paraelectric material. In future integrated circuits, the incorporation of such negative capacitance into MOSFET gate stacks would reduce the subthreshold slope, enabling low power operation and reduced self-heating.