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1.
ACS Appl Mater Interfaces ; 14(5): 7392-7404, 2022 Feb 09.
Artículo en Inglés | MEDLINE | ID: mdl-35099170

RESUMEN

Ruthenium may replace copper interconnects in next-generation very-large-scale integration (VLSI) circuits. However, interfacial bonding between Ru interconnect wires and surrounding dielectrics must be optimized to reduce thermal boundary resistance (TBR) for thermal management. In this study, various adhesion layers are employed to modify bonding at the Ru/SiO2 interface. The TBRs of film stacks are measured using the frequency-domain thermoreflectance technique. TiN and TaN with high nitrogen contents significantly reduce the TBR of the Ru/SiO2 interface compared to common Ti and Ta adhesion layers. The adhesion layer thickness, on the other hand, has only minor effect on TBR when the thickness is within 2-10 nm. Hard X-ray photoelectron spectroscopy of deeply buried layers and interfaces quantitatively reveals that the decrease in TBR is attributed to the enhanced bonding of interfaces adjacent to the TaN adhesion layer, probably due to the electron transfer between the atoms at two sides of the interface. Simulations by a three-dimensional electrothermal finite element method demonstrate that decreasing the TBR leads to a significantly smaller temperature increase in the Ru interconnects. Our findings highlight the importance of TBR in the thermal management of VLSI circuits and pave the way for Ru interconnects to replace the current Cu-based ones.

2.
J Phys Chem B ; 125(39): 11044-11057, 2021 10 07.
Artículo en Inglés | MEDLINE | ID: mdl-34551255

RESUMEN

The adhesion and fracture behavior of tetraglycidyl-4,4'-diaminodiphenylmethane (TGDDM)/4,4'-diaminodiphenyl sulfone (44DDS)-bisphenol A diglycidyl ether (DGEBA)/44DDS layer interfaces were investigated by molecular dynamics (MD) simulation, mainly focusing on the role of covalent and noncovalent interactions. To accurately investigate the bond dissociation processes, the force field parameters of several bond potentials of the epoxy resin polymers were optimized by density functional theory calculations. In the MD simulations under a tensile load, small voids gradually developed without covalent bond dissociation in the plateau region. In the final large strain region, the stress rapidly increased with bond breaking, leading to failure. When the chemical bonds across the interface between the two layers were removed, the stress-strain curve in the initial elastic region was almost the same as that with interfacial bonds. This showed that the nonbonded interactions governed adhesion strength in the initial elastic region. In contrast, the bonded interactions at interfaces played important roles in the hardening regions because the bonded interactions made the major contribution to the fracture energies. We also investigated the effect of the etherification reaction in cross-linking. It was found that the etherification reaction mainly contributed to the behavior in the late region with large strain. These simulation results revealed that the nonbonded interactions, especially, van der Waals interactions, are important factors for adhesion of the different polymer layers in the small strain region up to the yield point.


Asunto(s)
Resinas Epoxi , Simulación de Dinámica Molecular , Polímeros
3.
ACS Appl Mater Interfaces ; 12(30): 34441-34450, 2020 Jul 29.
Artículo en Inglés | MEDLINE | ID: mdl-32635712

RESUMEN

In microthermoelectric generators (µTEGs), parasitic thermal resistance must be suppressed to increase the temperature difference across thermocouples for optimum power generation. A thermally conductive (TC) layer is typically used in µTEGs to guide the heat flow from the heat source to the hot junction of each thermocouple. In this study, we investigate the effect of the thermal boundary resistance (TBR) in metal/dielectric TC layers on the power generation of silicon nanowire (SiNW) µTEGs. We prepared various metal/adhesion/dielectric TC layers using different metal, adhesion, and dielectric layers and measured the thermal resistance using the frequency-domain thermoreflectance method. We found that the thermal resistance was significantly different, mainly due to the TBR of the metal/dielectric interfaces. Interface characterization highlights the significant role of the interfacial bonding strength and interdiffusion in TBR. We fabricated a prototype SiNW-µTEG with different TC layers for testing, finding that the power generation increased significantly when the thermal resistance of the TC layer was lowered. This study helps to understand the underlying physics of thermal transport at interfaces and provides a guideline for the design and fabrication of µTEGs to enhance power generation for effective energy harvesting.

4.
ACS Appl Mater Interfaces ; 12(19): 22347-22356, 2020 May 13.
Artículo en Inglés | MEDLINE | ID: mdl-32315529

RESUMEN

Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10-8 to 1 × 10-7 m2 K W-1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.

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