Coffee and metabolic phenotypes: A cross-sectional analysis of the Japan multi-institutional collaborative cohort (J-MICC) study.

BACKGROUND AND AIMS: To date, the relationship between coffee consumption and metabolic phenotypes has hardly been investigated and remains controversial. Therefore, the aim of this cross-sectional study is to examine the associations between coffee consumption and metabolic phenotypes in a Japanese population. METHODS AND RESULTS: We analyzed the data of 26,363 subjects (aged 35-69 years) in the baseline survey of the Japan Multi-Institutional Collaborative Cohort Study. Coffee consumption was assessed using a questionnaire. Metabolic Syndrome (MetS) was defined according to the Joint Interim Statement Criteria of 2009, using body mass index (BMI) instead of waist circumference. Subjects stratified by the presence or absence of obesity (normal weight: BMI <25 kg/m2; obesity: BMI ≥25 kg/m2) were classified by the number of MetS components (metabolically healthy: no components; metabolically unhealthy: one or more components) other than BMI. In multiple logistic regression analyses adjusted for sex, age, and other potential confounders, high coffee consumption (≥3 cups/day) was associated with a lower prevalence of MetS and metabolically unhealthy phenotypes both in normal weight (OR 0.83, 95% CI 0.76-0.90) and obese subjects (OR 0.83, 95% CI 0.69-0.99). Filtered/instant coffee consumption was inversely associated with the prevalence of MetS and metabolically unhealthy phenotypes, whereas canned/bottled/packed coffee consumption was not. CONCLUSION: The present results suggest that high coffee consumption, particularly filtered/instant coffee, is inversely associated with the prevalence of metabolically unhealthy phenotypes in both normal weight and obese Japanese adults.

Synapse-Neuron-Aware Training Scheme of Defect-Tolerant Neural Networks with Defective Memristor Crossbars.

To overcome the limitations of CMOS digital systems, emerging computing circuits such as memristor crossbars have been investigated as potential candidates for significantly increasing the speed and energy efficiency of next-generation computing systems, which are required for implementing future AI hardware. Unfortunately, manufacturing yield still remains a serious challenge in adopting memristor-based computing systems due to the limitations of immature fabrication technology. To compensate for malfunction of neural networks caused from the fabrication-related defects, a new crossbar training scheme combining the synapse-aware with the neuron-aware together is proposed in this paper, for optimizing the defect map size and the neural network's performance simultaneously. In the proposed scheme, the memristor crossbar's columns are divided into 3 groups, which are the severely-defective, moderately-defective, and normal columns, respectively. Here, each group is trained according to the trade-off relationship between the neural network's performance and the hardware overhead of defect-tolerant training. As a result of this group-based training method combining the neuron-aware with the synapse-aware, in this paper, the new scheme can be successful in improving the network's performance better than both the synapse-aware and the neuron-aware while minimizing its hardware burden. For example, when testing the defect percentage = 10% with MNIST dataset, the proposed scheme outperforms the synapse-aware and the neuron-aware by 3.8% and 3.4% for the number of crossbar's columns trained for synapse defects = 10 and 138 among 310, respectively, while maintaining the smaller memory size than the synapse-aware. When the trained columns = 138, the normalized memory size of the synapse-neuron-aware scheme can be smaller by 3.1% than the synapse-aware.

Associations of metabolic syndrome and metabolically unhealthy obesity with cancer mortality: The Japan Multi-Institutional Collaborative Cohort (J-MICC) study.

PURPOSE: The association between metabolic syndrome (MetS) and the risk of death from cancer is still a controversial issue. The purpose of this study was to examine the associations of MetS and metabolically unhealthy obesity (MUHO) with cancer mortality in a Japanese population. METHODS: We used data from the Japan Multi-Institutional Collaborative Cohort Study. The study population consisted of 28,554 eligible subjects (14,103 men and 14,451 women) aged 35-69 years. MetS was diagnosed based on the criteria of the National Cholesterol Education Program Adult Treatment Panel III (NCEP-ATP III) and the Japan Society for the Study of Obesity (JASSO), using the body mass index instead of waist circumference. The Cox proportional hazards analysis was used to estimate adjusted hazard ratios (HR) and 95% confidence intervals (CI) for total cancer mortality in relation to MetS and its components. Additionally, the associations of obesity and the metabolic health status with cancer mortality were examined. RESULTS: During an average 6.9-year follow-up, there were 192 deaths from cancer. The presence of MetS was significantly correlated with increased total cancer mortality when the JASSO criteria were used (HR = 1.51, 95% CI 1.04-2.21), but not when the NCEP-ATP III criteria were used (HR = 1.09, 95% CI 0.78-1.53). Metabolic risk factors, elevated fasting blood glucose, and MUHO were positively associated with cancer mortality (P <0.05). CONCLUSION: MetS diagnosed using the JASSO criteria and MUHO were associated with an increased risk of total cancer mortality in the Japanese population.

Memristor-CMOS Hybrid Neuron Circuit with Nonideal-Effect Correction Related to Parasitic Resistance for Binary-Memristor-Crossbar Neural Networks.

Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network's performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%.

Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training.

A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the memristors takes a very long time and consumes a large amount of power, because of the incremental behavior of memristor's program-verify scheme for the fine-tuning of memristor's conductance. To reduce the programming time and power, the partial gating scheme is proposed here to realize the partial training, where only some part of neurons are trained, which are more responsible in the recognition error. By retraining the part, rather than the entire crossbar, the programming time and power of memristor crossbar can be significantly reduced. The proposed scheme has been verified by CADENCE circuit simulation with the real memristor's Verilog-A model. When compared to retraining the entire crossbar, the loss of recognition rate of the partial gating scheme has been estimated only as small as 2.5% and 2.9%, for the MNIST and CIFAR-10 datasets, respectively. However, the programming time and power can be saved by 86% and 89.5% than the 100% retraining, respectively.

Hybrid Circuit of Memristor and Complementary Metal-Oxide-Semiconductor for Defect-Tolerant Spatial Pooling with Boost-Factor Adjustment.

Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain's neocortical operation. However, mimicking the brain's neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain's architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM's spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM's SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar.

Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons.

As a software framework, Hierarchical Temporal Memory (HTM) has been developed to perform the brain's neocortical functions, such as spatial and temporal pooling. However, it should be realized with hardware not software not only to mimic the neocortical function but also to exploit its architectural benefit. To do so, we propose a new memristor-CMOS (Complementary Metal-Oxide-Semiconductor) hybrid circuit of temporal-pooling here, which is composed of the input-layer and output-layer neurons mimicking the neocortex. In the hybrid circuit, the input-layer neurons have the proximal and basal/distal dendrites to combine sensory information with the temporal/location information from the brain's hippocampus. Using the same crossbar architecture, the output-layer neurons can perform a prediction by integrating the temporal information on the basal/distal dendrites. For training the proposed circuit, we used only simple Hebbian learning, not the complicated backpropagation algorithm. Due to the simple hardware of Hebbian learning, the proposed hybrid circuit can be very suitable to online learning. The proposed memristor-CMOS hybrid circuit has been verified by the circuit simulation using the real memristor model. The proposed circuit has been verified to predict both the ordinal and out-of-order sequences. In addition, the proposed circuit has been tested with the external noise and memristance variation.

Asymmetrical Training Scheme of Binary-Memristor-Crossbar-Based Neural Networks for Energy-Efficient Edge-Computing Nanoscale Systems.

For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training the memristor crossbar, because the program-verify scheme of memristor-programming is based on the incremental programming pulses, where many programming and verifying pulses are repeated until the target conductance. Thus, this reduces the programming time and power is very essential for energy-efficient and fast training of memristor networks. In this paper, we compared four different programming schemes, which are F-F, C-F, F-C, and C-C, respectively. C-C means both HRS and LRS are coarse-programmed. C-F has the coarse-programmed HRS and fine LRS, respectively. F-C is vice versa of C-F. In F-F, both HRS and LRS are fine-programmed. Comparing the error-energy products among the four schemes, C-F shows the minimum error with the minimum energy consumption. The asymmetrical coarse HRS and fine LRS can reduce the time and energy during the crossbar training significantly, because only LRS is fine-programmed. Moreover, the asymmetrical C-F can maintain the network's error as small as F-F, which is due to the coarse-programmed HRS that slightly degrades the error.

Practical asymmetric enzymatic reduction through discovery of a dehydrogenase-compatible biphasic reaction media.

[reaction: see text] An enzyme-compatible biphasic reaction media for the asymmetric biocatalytic reduction of ketones with in situ cofactor regeneration has been developed. In this biphasic reaction media, which is advantageous for reactions at higher substrate concentrations, both enzymes (alcohol dehydrogenase and FDH from Candida boidinii) remain stable. The reductions with poorly water-soluble ketones were carried out at substrate concentrations of 10-200 mM, and the optically active (S)-alcohols were formed with moderate to good conversions and with up to >99% ee.