Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes.

The deluge of sensors and data generating devices has driven a paradigm shift in modern computing from arithmetic-logic centric to data-centric processing. Data-centric processing require innovations at the device level to enable novel compute-in-memory (CIM) operations. A key challenge in the construction of CIM architectures is the conflicting trade-off between the performance and their flexibility for various essential data operations. Here, we present a transistor-free CIM architecture that permits storage, search, and neural network operations on sub-50 nm thick Aluminum Scandium Nitride ferroelectric diodes (FeDs). Our circuit designs and devices can be directly integrated on top of Silicon microprocessors in a scalable process. By leveraging the field-programmability, nonvolatility, and nonlinearity of FeDs, search operations are demonstrated with a cell footprint <0.12 µm2 when projected onto 45 nm node technology. We further demonstrate neural network operations with 4-bit operation using FeDs. Our results highlight FeDs as candidates for efficient and multifunctional CIM platforms.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory.

Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

A Multi-Beam Shared-Inductor Reconfigurable Voltage/SECE Mode Piezoelectric Energy Harvesting Interface Circuit.

This paper presents an autonomous multi-input (multi-beam) reconfigurable power-management chip for optimal energy harvesting from weak multi-axial human motion using a multi-beam piezoelectric energy harvester (PEH). The proposed chip adaptively operates in either voltage-mode or synchronous-electrical-charge-extraction-mode (VM-SECE) to improve overall efficiency, extract maximum energy regardless of the PEH beams' impedance/voltage/frequency variations, and protect the chip against large inputs, eliminating the need for high-voltage processes. It can simultaneously harvest energy from up to 6 beams using only one shared off-chip inductor. It uses an active negative voltage converter to extend the input-voltage range to as low as 35 mV. In addition, an active voltage doubler with a small footprint is implemented for faster cold start. A prototype VM-SECE chip was fabricated in a 0.35-µm 2P4M standard CMOS process occupying 1.9 mm2 active area. To fully characterize the chip performance, it was tested with both a commercial single-beam PEH and a custom-made PEH with five mechanically plucked thin-film beams. With the commercial PEH, compared to an on-chip full-wave active rectifier (FAR) with 95.6% efficiency, the VM-SECE chip harvested 3.28x more power for shock inputs at 1 Hz frequency and 4.39 g acceleration. With the custom 5-beam PEH for a pseudo-walking condition, compared to the on-chip FAR, the VM-SECE chip harvested 1.59x and 2.38x more power for 1-and 5-beam operations, respectively.