A Hardware-Friendly High-Precision CNN Pruning Method and Its FPGA Implementation.

To address the problems of large storage requirements, computational pressure, untimely data supply of off-chip memory, and low computational efficiency during hardware deployment due to the large number of convolutional neural network (CNN) parameters, we developed an innovative hardware-friendly CNN pruning method called KRP, which prunes the convolutional kernel on a row scale. A new retraining method based on LR tracking was used to obtain a CNN model with both a high pruning rate and accuracy. Furthermore, we designed a high-performance convolutional computation module on the FPGA platform to help deploy KRP pruning models. The results of comparative experiments on CNNs such as VGG and ResNet showed that KRP has higher accuracy than most pruning methods. At the same time, the KRP method, together with the GSNQ quantization method developed in our previous study, forms a high-precision hardware-friendly network compression framework that can achieve "lossless" CNN compression with a 27× reduction in network model storage. The results of the comparative experiments on the FPGA showed that the KRP pruning method not only requires much less storage space, but also helps to reduce the on-chip hardware resource consumption by more than half and effectively improves the parallelism of the model in FPGAs with a strong hardware-friendly feature. This study provides more ideas for the application of CNNs in the field of edge computing.

Improved Active Disturbance Rejection Double Closed-Loop Control of a Rotary-Type VCM in a Moving Mirror Control System.

Aiming to address the problem of moving mirror speed fluctuations in moving mirror control systems, an improved active disturbance rejection double closed-loop controller (IADR-DCLC) is proposed and verified by simulation to realize the high-performance control of a moving mirror control system. First, the mathematical model of a rotary-type voice coil motor (RT VCM) is established, and the relationship between the angular velocity of the RT VCM and the optical path scanning velocity is analyzed. Second, in order to suppress the model uncertainty and external disturbance of the system, an improved active disturbance rejection controller (IADRC) is proposed. Compared with a conventional ADRC, the tracking differentiator of the proposed IADRC is replaced with desired signal optimization (DSO), and the actual speed is introduced to the extended state observer (ESO). The IADRC is used in the position-speed double closed-loop control model. Finally, the simulation results show that the IADR-DCLC has not only a good tracking effect but also a good anti-interference ability and can meet the requirements of the moving mirror control system for the uniformity of optical-path scanning speed and accurate control of the position of the moving mirror.

A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs and Its FPGA Implementation.

To address the problems of convolutional neural networks (CNNs) consuming more hardware resources (such as DSPs and RAMs on FPGAs) and their accuracy, efficiency, and resources being difficult to balance, meaning they cannot meet the requirements of industrial applications, we proposed an innovative low-bit power-of-two quantization method: the global sign-based network quantization (GSNQ). This method involves designing different quantization ranges according to the sign of the weights, which can provide a larger quantization-value range. Combined with the fine-grained and multi-scale global retraining method proposed in this paper, the accuracy loss of low-bit quantization can be effectively reduced. We also proposed a novel convolutional algorithm using shift operations to replace multiplication to help to deploy the GSNQ quantized models on FPGAs. Quantization comparison experiments performed on LeNet-5, AlexNet, VGG-Net, ResNet, and GoogLeNet showed that GSNQ has higher accuracy than most existing methods and achieves "lossless" quantization (i.e., the accuracy of the quantized CNN model is higher than the baseline) at low-bit quantization in most cases. FPGA comparison experiments showed that our convolutional algorithm does not occupy on-chip DSPs, and it also has a low comprehensive occupancy in terms of on-chip LUTs and FFs, which can effectively improve the computational parallelism, and this proves that GSNQ has good hardware-adaptation capability. This study provides theoretical and experimental support for the industrial application of CNNs.