Identifying atomically thin isolated-band channels for intrinsic steep-slope transistors by high-throughput study.

Developing low-power FETs holds significant importance in advancing logic circuits, especially as the feature size of MOSFETs approaches sub-10 nanometers. However, this has been restricted by the thermionic limitation of SS, which is limited to 60 mV per decade at room temperature. Herein, we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize sub-thermionic SS in MOSFETs. Through high-throughput calculations, we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport potential. This guides us to screen 192 candidates from the 2D material database comprising 1608 systems. Additionally, the physical relationship between the sub-thermionic transport performances and electronic structures is further revealed, which enables us to predict 15 systems with promising device performances for low-power applications with supply voltage below 0.5 V. This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimental exploration of intrinsic steep-slope MOSFETs.

Buried graphene heterostructures for electrostatic doping of low-dimensional materials.

The fabrication and characterization of steep slope transistor devices based on low-dimensional materials requires precise electrostatic doping profiles with steep spatial gradients in order to maintain maximum control over the channel. In this proof-of-concept study we present a versatile graphene heterostructure platform with three buried individually addressable gate electrodes. The platform is based on a vertical stack of embedded titanium and graphene separated by an intermediate oxide to provide an almost planar surface. We demonstrate the functionality and advantages of the platform by exploring transfer and output characteristics at different temperatures of carbon nanotube field-effect transistors with different electrostatic doping configurations. Furthermore, we back up the concept with finite element simulations to investigate the surface potential. The presented heterostructure is an ideal platform for analysis of electrostatic doping of low-dimensional materials for novel low-power transistor devices.

Steep-slope transistors enabled with 2D quantum coupling stacks.

As down scaling of transistors continues, there is a growing interest in developing steep-slope transistors with reduced subthreshold slope (SS) below the Boltzmann limit. In this work, we successfully fabricated steep-slope MoS2transistors by incorporating a graphene layer, inserted in the gate stack. For our comprehensive study, we have applied density functional theory to simulate and calculate the change of SS effected by different 2D quantum materials, including graphene, germanene and 2D topological insulators, inserted within the gate dielectric. This theoretical study showed that graphene/MoS2devices had steep SS (27.2 mV/decade), validating our experimental approach (49.2 mV/decade). Furthermore, the simulations demonstrated very steep SS (8.6 mV/decade) in WTe2/MoS2devices. We conclude that appropriate combination of various 2D quantum materials for the gate-channel stacks, leads to steep SS and is an effective method to extend the scaling of transistors with exceptional performance.

Ferroelectric Nanogap-Based Steep-Slope Ambipolar Transistor.

The subthreshold swing (SS) of metal-oxide-semiconductor field-effect transistors is limited to 60 mV dec-1 at room temperature by the Boltzmann tyranny, which restricts the scaling of the supply voltage. A nanogap-based transistor employs a switchable nanoscale air gap as the channel, offering a steep-slope switching process. Meanwhile, nanogaps featuring even sub-3 nm can efficiently block the current flow, exhibiting the potential for tackling the short-channel effect. Here, an electrically switchable ferroelectric nanogap to construct steep-slope transistors, is exploited. An average SS of 15.9 mV dec-1 across 5 orders and a minimum SS of 13.23 mV dec-1 are obtained in the high current density range. The transistor exhibits excellent performance with near-zero off-state leakage current and a maximum on-state current of 202 µA µm-1 at VDS  = 0.5 V. In addition, the transistor can turn off with either a positive or negative increase in the gate voltage, exhibiting ambipolar characteristics.

Two-Dimensional Cold Electron Transport for Steep-Slope Transistors.

Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the "Boltzmann tyranny" that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic refrigeration effect with an effective electron temperature of ∼145 K in the monolayer MoS2, which enables the transport factor lowering and thus the steep-slope switching (across for three decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 µA/µm) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the potential of a 2D Dirac-source cold electron transistor as a steep-slope transistor concept for future energy-efficient nanoelectronics.

A New Opportunity for 2D van der Waals Heterostructures: Making Steep-Slope Transistors.

The use of a foreign metallic cold source (CS) has recently been proposed as a promising approach toward the steep-slope field-effect-transistor (FET). In addition to the selection of source material with desired density of states-energy relation (D(E)), engineering the source:channel interface for gate-tunable channel-barrier is crucial to CS-FETs. However, conventional metal:semiconductor (MS) interfaces generally suffer from strong Fermi-level pinning due to the inevitable chemical disorder and defect-induced gap states, precluding the gate tunability of the barriers. By comprehensive materials and device modeling at the atomic scale, it is reported that 2D van der Waals (vdW) MS interfaces, with their atomic sharpness and cleanness, can be considered as general ingredients for CS-FETs. As test cases, InSe-based n-type FETs are studied. It is found that graphene can be spontaneously p-type doped along with slightly opened bandgap around the Dirac-point by interfacing with InSe, resulting in superexponentially decaying hot carrier density with increasing n-type channel-barrier. Moreover, the D(E) relations suggest that 2D transition-metal dichalcogenides and 2D transition-metal carbides are a rich library of CS materials. Graphene, Cd3 C2 , T-VTe2 , H-VTe2 , and H-TaTe2 CSs lead to subthreshold swing below 60 mV dec-1 . This work broadens the application potentials of 2D vdW MS heterostructures and serves as a springboard for more studies on low-power electronics based on 2D materials.