A Design Method and Application of Meta-Surface-Based Arbitrary Passband Filter for Terahertz Communication.

A meta-surface-based arbitrary bandwidth filter realization method for terahertz (THz) future communications is presented. The approach involves integrating a meta-surface-based bandstop filter into an ultra-wideband (UWB) bandpass filter and adjusting the operating frequency range of the meta-surface bandstop filter to realize the design of arbitrary bandwidth filters. It effectively addresses the complexity of designing traditional arbitrary bandwidth filters and the challenges in achieving impedance matching. To underscore its practicality, the paper employs silicon substrate integrated gap waveguide (SSIGW) and this method to craft a THz filter. To begin, design equations for electromagnetic band gap (EBG) structures were developed in accordance with the requirements of through-silicon via (TSV) and applied to the design of the SSIGW. Subsequently, this article employs equivalent transmission line models and equivalent circuits to conduct theoretical analyses for both the UWB passband and the meta-surface stopband portions. The proposed THz filter boasts a center frequency of 0.151 THz, a relative bandwidth of 6.9%, insertion loss below 0.68 dB, and stopbands exceeding 20 GHz in both upper and lower ranges. The in-band group delay is 0.119 ± 0.048 ns. Compared to reported THz filters, the SSIGW filter boasts advantages such as low loss and minimal delay, making it even more suitable for future wireless communication.

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array.

In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.

Multimode Optical Interconnects on Silicon Interposer Enable Confidential Hardware-to-Hardware Communication.

Following Moore's law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 µm long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks.

Modeling and Validation of Total Ionizing Dose Effect on the TSVs in RF Microsystem.

Radio frequency (RF) systems utilizing through-silicon vias (TSVs) have been widely used in the aerospace and nuclear industry, which means that studying the total ionizing dose (TID) effect on TSV structures has become necessary. To investigate the TID effect on TSV structures, a 1D TSV capacitance model was established in COMSOL Multiphysics (COMSOL), and the impact of irradiation was simulated. Then, three types of TSV components were designed, and an irradiation experiment based on them was conducted, to validate the simulation results. After irradiation, the S21 degraded for 0.2 dB, 0.6 dB, and 0.8 dB, at the irradiation dose of 30 krad (Si), 90 krad (Si), 150 krad (Si), respectively. The variation trend was consistent with the simulation in the high-frequency structure simulator (HFSS), and the effect of irradiation on the TSV component was nonlinear. With the increase in the irradiation dose, the S21 of TSV components deteriorated, while the variation of S21 decreased. The simulation and irradiation experiment validated a relatively accurate method for assessing the RF systems' performance under an irradiation environment, and the TID effect on structures similar to TSVs in RF systems, such as through-silicon capacitors.

Design of a Novel Compact Bandpass Filter Based on Low-Cost Through-Silicon-Via Technology.

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices.

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects.

Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor's data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias.

An accurate equivalent thermal model is proposed to calculate the equivalent thermal conductivity (ETC) of shield differential through-silicon via (SDTSV). The mathematical expressions of ETC in both horizontal and vertical directions are deduced by considering the anisotropy of SDTSV. The accuracy of the proposed model is verified by the finite element method (FEM), and the average errors of temperature along the X-axis, Y-axis, diagonal line, and vertical directions are 1.37%, 3.42%, 1.76%, and 0.40%, respectively. Compared with COMSOL, the proposed model greatly improves the computational efficiency. Moreover, the effects of different parameters on the thermal distribution of SDTSV are also investigated. The thermal conductivity is decreased with the increase in thickness of SiO2. With the increase in pitch, the maximum temperature of SDTSV increases very slowly when ß = 0° , and decreases very slowly when ß = 90°. The proposed model can be used to accurately and quickly describe the thermal distribution of SDTSV, which has a great prospect in the design of 3D IC.

Effect of Pulse Current and Pre-annealing on Thermal Extrusion of Cu in Through-Silicon via (TSV).

Thermal stress induced by annealing the Cu filling of through-silicon vias (TSVs) requires further investigation as it can inhibit the performance of semiconductor devices. This study reports the filling behavior of TSVs prepared using direct current and pulse current Cu electrodeposition with and without pre-annealing. The thermal extrusion of Cu inside the TSVs was studied by observing the extrusion behavior after annealing and the changes in grain orientation using scanning electron microscopy and electron backscatter diffraction. The bottom-up filling ratio achieved by the direct current approach decreased because the current was used both to fill the TSV and to grow bump defects on the top surface of the wafer. In contrast, pulse current electrodeposition yielded an improved TSV bottom-up filling ratio and no bump defects, which is attributable to strong suppression and thin diffusion layer. Moreover, Cu deposited with a pulse current exhibited lesser thermal extrusion, which was attributed to the formation of nanotwins and a change in the grain orientation from random to (101). Based on the results, thermal extrusion of the total area of the TSVs could be obtained by pulse current electrodeposition with pre-annealing.

Quartz tuning fork based three-dimensional topography imaging for sidewall with blind features.

Atomic force microscopy has a tremendous number of applications in a wide variety of fields, particularly in the semiconductor area for the 3D-stacked device. Imaging three-dimensional (3D) structures with blind features has progressively become a critical technique. Recently, a 3D-atomic force microscopy (AFM) technique has been proposed to image 3D features, especially those having sharp apices, like silicon pillars. However, the scanning strategy has drawbacks, such as long scanning time, and unstable operation, based on the premature algorithm. Herein, an improved 3D-AFM algorithm is reported that overcomes the aforementioned problems by an intelligent 3D scanning algorithm that incorporates sidewall history tracking, troubleshooting for sharp sidewall and sticking, and reactive direction adjustment. The proposed algorithm enables the 3D imagery of ZnO nano-rods and silicon nano-pillars to be achieved by using a high aspect-ratio multiwall carbon nanotube-based AFM probe, without time-consuming disorientation. This study establishes a method to construct a 3D image of arbitrary shape in reduced scanning time.

Design and Fabrication Technology of Low Profile Tactile Sensor with Digital Interface for Whole Body Robot Skin.

Covering a whole surface of a robot with tiny sensors which can measure local pressure and transmit the data through a network is an ideal solution to give an artificial skin to robots to improve a capability of action and safety. The crucial technological barrier is to package force sensor and communication function in a small volume. In this paper, we propose the novel device structure based on a wafer bonding technology to integrate and package capacitive force sensor using silicon diaphragm and an integrated circuit separately manufactured. Unique fabrication processes are developed, such as the feed-through forming using a dicing process, a planarization of the Benzocyclobutene (BCB) polymer filled in the feed-through and a wafer bonding to stack silicon diaphragm onto ASIC (application specific integrated circuit) wafer. The ASIC used in this paper has a capacitance measurement circuit and a digital communication interface mimicking a tactile receptor of a human. We successfully integrated the force sensor and the ASIC into a 2.5 × 2.5 × 0.32.5×2.5×0.3 mm die and confirmed autonomously transmitted packets which contain digital sensing data with the linear force sensitivity of 57,640 Hz/N and 10 mN of data fluctuation. A small stray capacitance of 1.33 pF is achieved by use of 10 µm thick BCB isolation layer and this minimum package structure.

Bottom-Up Electrodeposition of Large-Scale Nanotwinned Copper within 3D Through Silicon Via.

This paper is the first to report a large-scale directcurrent electrodeposition of columnar nanotwinned copper within through silicon via (TSV) with a high aspect ratio (~4). With this newly developed technique, void-free nanotwinned copper array could be fabricated in low current density (30 mA/cm²) and convection conditions (300 rpm), which are the preconditions for copper deposition with a uniform deep-hole microstructure. The microstructure of a whole cross-section of deposited copper array was made up of (111) orientated columnar grains with parallel nanoscale twins that had thicknesses of about 22 nm. The hardness was also uniform along the growth direction, with 2.34 and 2.68 GPa for the top and bottom of the TSV, respectively. The gelatin additive is also first reported hereas a key factor in forming nanoscale twins by adsorbing on the cathode surface, in order to enhance the overpotential for cathodic reaction during the copper deposition process.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Inkjet printing technology for increasing the I/O density of 3D TSV interposers.

Interposers with through-silicon vias (TSVs) play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems. In the current practice of fabricating interposers, solder balls are placed next to the vias; however, this approach requires a large foot print for the input/output (I/O) connections. Therefore, in this study, we investigate the possibility of placing the solder balls directly on top of the vias, thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections. To reach this goal, inkjet printing (that is, piezo and super inkjet) was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer. The under bump metallization (UBM) pads were also successfully printed with inkjet technology on top of the polymer-filled vias, using either Ag or Au inks. The reliability of the TSV interposers was investigated by a temperature cycling stress test (-40 °C to +125 °C). The stress test showed no impact on DC resistance of the TSVs; however, shrinkage and delamination of the polymer was observed, along with some micro-cracks in the UBM pads. For proof of concept, SnAgCu-based solder balls were jetted on the UBM pads.

A Study on Electrical Reliability Criterion on Through Silicon Via Packaging.

Three-dimensional (3D) structure with through silicon via (TSV) technology is emerging as a key issue in microelectronic packaging industry, and electrical reliability has become one of the main technical subjects for the TSV designs. However, criteria used for TSV reliability tests have not been consistent in the literature, so that the criterion itself becomes a technical argument. To this end, this paper first performed several different reliability tests on the testing packaging with TSV chains, then statistically analyzed the experimental data with different failure criteria on resistance increasing, and finally constructed the Weibull failure curves with parameter extractions. After comparing the results, it is suggested that using different criteria may lead to the same failure mode on Weibull analyses, and 65% of failed devices are recommended as a suitable termination for reliability tests.

X-ray nanodiffraction analysis of stress oscillations in a W thin film on through-silicon via.

Synchrotron X-ray nanodiffraction is used to analyse residual stress distributions in a 200 nm-thick W film deposited on the scalloped inner wall of a through-silicon via. The diffraction data are evaluated using a novel dedicated methodology which allows the quantification of axial and tangential stress components under the condition that radial stresses are negligible. The results reveal oscillatory axial stresses in the range of ∼445-885 MPa, with a distribution that correlates well with the scallop wavelength and morphology, as well as nearly constant tangential stresses of ∼800 MPa. The discrepancy with larger stress values obtained from a finite-element model, as well as from a blanket W film, is attributed to the morphology and microstructural nature of the W film in the via.

Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding.

This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach.