Acoustic-driven magnetic skyrmion motion.

Magnetic skyrmions have great potential for developing novel spintronic devices. The electrical manipulation of skyrmions has mainly relied on current-induced spin-orbit torques. Recently, it was suggested that the skyrmions could be more efficiently manipulated by surface acoustic waves (SAWs), an elastic wave that can couple with magnetic moment via the magnetoelastic effect. Here, by designing on-chip piezoelectric transducers that produce propagating SAW pulses, we experimentally demonstrate the directional motion of Néel-type skyrmions in Ta/CoFeB/MgO/Ta multilayers. We find that the shear horizontal wave effectively drives the motion of skyrmions, whereas the elastic wave with longitudinal and shear vertical displacements (Rayleigh wave) cannot produce the motion of skyrmions. A longitudinal motion along the SAW propagation direction and a transverse motion due to topological charge are simultaneously observed and further confirmed by our micromagnetic simulations. This work demonstrates that acoustic waves could be another promising approach for manipulating skyrmions, which could offer new opportunities for ultra-low power skyrmionics.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning.

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Edge learning using a fully integrated neuro-inspired memristor chip.

Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Energy-efficient high-fidelity image reconstruction with memristor arrays for medical diagnosis.

Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning.

The growing computational demand in artificial intelligence calls for hardware solutions that are capable of in situ machine learning, where both training and inference are performed by edge computation. This not only requires extremely energy-efficient architecture (such as in-memory computing) but also memory hardware with tunable properties to simultaneously meet the demand for training and inference. Here we report a duplex device structure based on a ferroelectric field-effect transistor and an atomically thin MoS2 channel, and realize a universal in-memory computing architecture for in situ learning. By exploiting the tunability of the ferroelectric energy landscape, the duplex building block demonstrates an overall excellent performance in endurance (>1013), retention (>10 years), speed (4.8 ns) and energy consumption (22.7 fJ bit-1 µm-2). We implemented a hardware neural network using arrays of two-transistors-one-duplex ferroelectric field-effect transistor cells and achieved 99.86% accuracy in a nonlinear localization task with in situ trained weights. Simulations show that the proposed device architecture could achieve the same level of performance as a graphics processing unit under notably improved energy efficiency. Our device core can be combined with silicon circuitry through three-dimensional heterogeneous integration to give a hardware solution towards general edge intelligence.

Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

A Memristors-Based Dendritic Neuron for High-Efficiency Spatial-Temporal Information Processing.

Diverse microscopic ionic dynamics help mediate the ability of a biological neural network to handle complex tasks with low energy consumption. Thus, rich internal ionic dynamics in memristors based on transition metal oxide are expected to provide a unique and useful platform for implementing energy-efficient neuromorphic computing. To this end, a titanium oxide (TiOx )-based interface-type dynamic memristor and an niobium oxide (NbOx )-based Mott memristor are integrated as an artificial dendrite and spike-firing soma, respectively, to construct a dendritic neuron unit for realizing high-efficiency spatial-temporal information processing. Further, a dendritic neural network is hardware-implemented for spatial-temporal information processing to highlight the computational advantages achieved by incorporating dendritic functions in the network. Human motion recognition is demonstrated using the Nanyang Technological University-Red Green Blue (NTU-RGB) dataset as a benchmark spatial-temporal task; it shows a nearly 20% improvement in accuracy for the memristors-based hardware incorporating dendrites and a 1000× advantage in power efficiency compared to that of the graphics processing unit (GPU). The dendritic neuron developed in this study can be considered a critical building block for implementing more bio-plausible neural networks that can manage complex spatial-temporal tasks with high efficiency.

Three-Dimensional Reconstruction of Conductive Filaments in HfOx -Based Memristor.

HfOx -based memristor has been studied extensively as one of the most promising memories for the excellent nonvolatile data storage and computing-in-memory capabilities. However, the resistive switching mechanism, relying on the formation and rupture of conductive filaments (CFs) during device operations, is still under debate. In this work, the CFs with different morphologies after different operations-forming, set, and reset-are clearly revealed for the first time by 3D reconstruction of conductive atomic force microscopy (c-AFM) images. Intriguingly, multiple CFs are successfully observed in HfOx -based memristor devices with three different resistive states. CFs after forming, set, and reset exhibit the typical morphologies of hourglass, inverted-cone, and short-cone, respectively. The rupture location of CFs after the reset operation is also observed clearly. These findings reveal the microscopic behaviors underlying the resistive switching, which could pave the road to design and optimize oxide-based memristors for both memory and computing applications.

Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.

In the long pursuit of smart robotics, it has been envisioned to empower robots with human-like senses, especially vision and touch. While tremendous progress has been made in image sensors and computer vision over the past decades, tactile sense abilities are lagging behind due to the lack of large-scale flexible tactile sensor array with high sensitivity, high spatial resolution, and fast response. In this work, we have demonstrated a 64 × 64 flexible tactile sensor array with a record-high spatial resolution of 0.9 mm (equivalently 28.2 pixels per inch) by integrating a high-performance piezoresistive film (PRF) with a large-area active matrix of carbon nanotube thin-film transistors. PRF with self-formed microstructures exhibited high pressure-sensitivity of ∼385 kPa-1 for multi-walled carbon nanotubes concentration of 6%, while the 14% one exhibited fast response time of ∼3 ms, good linearity, broad detection range beyond 1400 kPa, and excellent cyclability over 3000 cycles. Using this fully integrated tactile sensor array, the footprint maps of an artificial honeybee were clearly identified. Furthermore, we hardware-implemented a smart tactile system by integrating the PRF-based sensor array with a memristor-based computing-in-memory chip to record and recognize handwritten digits and Chinese calligraphy, achieving high classification accuracies of 98.8% and 97.3% in hardware, respectively. The integration of sensor networks with deep learning hardware may enable edge or near-sensor computing with significantly reduced power consumption and latency. Our work could empower the building of large-scale intelligent sensor networks for next-generation smart robotics.

A compute-in-memory chip based on resistive random-access memory.

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Concealable physically unclonable function chip with a memristor array.

A physically unclonable function (PUF) is a creditable and lightweight solution to the mistrust in billions of Internet of Things devices. Because of this remarkable importance, PUF need to be immune to multifarious attack means. Making the PUF concealable is considered an effective countermeasure but it is not feasible for existing PUF designs. The bottleneck is finding a reproducible randomness source that supports repeatable concealment and accurate recovery of the PUF data. In this work, we experimentally demonstrate a concealable PUF at the chip level with an integrated memristor array and peripherals. The correlated filamentary switching characteristic of the hafnium oxide (HfOx)-based memristor is used to achieve PUF concealment/recovery with SET/RESET operations efficiently. PUF recovery with a zero-bit error rate and remarkable attack resistance are achieved simultaneously with negligible circuit overhead. This concealable PUF provides a promising opportunity to build memristive hardware systems with effective security in the near future.

Memristor-based analogue computing for brain-inspired sound localization with in situ training.

The human nervous system senses the physical world in an analogue but efficient way. As a crucial ability of the human brain, sound localization is a representative analogue computing task and often employed in virtual auditory systems. Different from well-demonstrated classification applications, all output neurons in localization tasks contribute to the predicted direction, introducing much higher challenges for hardware demonstration with memristor arrays. In this work, with the proposed multi-threshold-update scheme, we experimentally demonstrate the in-situ learning ability of the sound localization function in a 1K analogue memristor array. The experimental and evaluation results reveal that the scheme improves the training accuracy by ∼45.7% compared to the existing method and reduces the energy consumption by ∼184× relative to the previous work. This work represents a significant advance towards memristor-based auditory localization system with low energy consumption and high performance.

Rotating neurons for all-analog implementation of cyclic reservoir computing.

Hardware implementation in resource-efficient reservoir computing is of great interest for neuromorphic engineering. Recently, various devices have been explored to implement hardware-based reservoirs. However, most studies were mainly focused on the reservoir layer, whereas an end-to-end reservoir architecture has yet to be developed. Here, we propose a versatile method for implementing cyclic reservoirs using rotating elements integrated with signal-driven dynamic neurons, whose equivalence to standard cyclic reservoir algorithm is mathematically proven. Simulations show that the rotating neuron reservoir achieves record-low errors in a nonlinear system approximation benchmark. Furthermore, a hardware prototype was developed for near-sensor computing, chaotic time-series prediction and handwriting classification. By integrating a memristor array as a fully-connected output layer, the all-analog reservoir computing system achieves 94.0% accuracy, while simulation shows >1000× lower system-level power than prior works. Therefore, our work demonstrates an elegant rotation-based architecture that explores hardware physics as computational resources for high-performance reservoir computing.

Memristive Behaviors Dominated by Reversible Nucleation Dynamics of Phase-Change Nanoclusters.

One of the important steps for realizing artificial intelligence is identifying elementary units that are beneficial for neural network construction. A type of memristive behavior in which phase-change nanoclusters nucleate adaptively in two adjacent dielectric layers with distinct distribution patterns is demonstrated. This memristive system responds in potentiation to increased stimulation strength and fire action potential after threshold stimulation. Reversible nucleation of phase-change nanoclusters is confirmed after both in situ and ex situ examinations using high-resolution transmission electron microscopy. The dynamics at the nanoscale level dominates the actions of the two dielectric layers. The oscillation response over a long period is due to the competition between crystalline and amorphous phases in the layer near the bottom electrode. Weight mutation, that is, action potential firing, is caused by the blockage of the filament in the layer near the top electrode. The memristive system is compact and able to execute complicated functions of a complete neuron and performs an important role in neuromorphic computing.

Toward memristive in-memory computing: principles and applications.

With the rapid growth of computer science and big data, the traditional von Neumann architecture suffers the aggravating data communication costs due to the separated structure of the processing units and memories. Memristive in-memory computing paradigm is considered as a prominent candidate to address these issues, and plentiful applications have been demonstrated and verified. These applications can be broadly categorized into two major types: soft computing that can tolerant uncertain and imprecise results, and hard computing that emphasizes explicit and precise numerical results for each task, leading to different requirements on the computational accuracies and the corresponding hardware solutions. In this review, we conduct a thorough survey of the recent advances of memristive in-memory computing applications, both on the soft computing type that focuses on artificial neural networks and other machine learning algorithms, and the hard computing type that includes scientific computing and digital image processing. At the end of the review, we discuss the remaining challenges and future opportunities of memristive in-memory computing in the incoming Artificial Intelligence of Things era.

Analog memristive synapse based on topotactic phase transition for high-performance neuromorphic computing and neural network pruning.

Inspired by the human brain, nonvolatile memories (NVMs)-based neuromorphic computing emerges as a promising paradigm to build power-efficient computing hardware for artificial intelligence. However, existing NVMs still suffer from physically imperfect device characteristics. In this work, a topotactic phase transition random-access memory (TPT-RAM) with a unique diffusive nonvolatile dual mode based on SrCoO x is demonstrated. The reversible phase transition of SrCoO x is well controlled by oxygen ion migrations along the highly ordered oxygen vacancy channels, enabling reproducible analog switching characteristics with reduced variability. Combining density functional theory and kinetic Monte Carlo simulations, the orientation-dependent switching mechanism of TPT-RAM is investigated synergistically. Furthermore, the dual-mode TPT-RAM is used to mimic the selective stabilization of developing synapses and implement neural network pruning, reducing ~84.2% of redundant synapses while improving the image classification accuracy to 99%. Our work points out a new direction to design bioplausible memristive synapses for neuromorphic computing.

Observation of the antiferromagnetic spin Hall effect.

The discovery of the spin Hall effect1 enabled the efficient generation and manipulation of the spin current. More recently, the magnetic spin Hall effect2,3 was observed in non-collinear antiferromagnets, where the spin conservation is broken due to the non-collinear spin configuration. This provides a unique opportunity to control the spin current and relevant device performance with controllable magnetization. Here, we report a magnetic spin Hall effect in a collinear antiferromagnet, Mn2Au. The spin currents are generated at two spin sublattices with broken spatial symmetry, and the antiparallel antiferromagnetic moments play an important role. Therefore, we term this effect the 'antiferromagnetic spin Hall effect'. The out-of-plane spins from the antiferromagnetic spin Hall effect are favourable for the efficient switching of perpendicular magnetized devices, which is required for high-density applications. The antiferromagnetic spin Hall effect adds another twist to the atomic-level control of spin currents via the antiferromagnetic spin structure.

Ratio-based multi-level resistive memory cells.

Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to [Formula: see text] at the best case and [Formula: see text] at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell's programming time and programming energy by up 5-10[Formula: see text], while achieving the same bit error probability.