Effects of thermal annealing on analog resistive switching behavior in bilayer HfO2/ZnO synaptic devices: the role of ZnO grain boundaries.

The effects of thermal annealing on analog resistive switching behavior in bilayer HfO2/ZnO synaptic devices were investigated. The annealed active ZnO layer between the top Pd electrode and the HfO2 layer exhibited electroforming-free resistive switching. In particular, the switching uniformity, stability, and reliability of the synaptic devices were dramatically improved via thermal annealing at 600 °C atomic force microscopy and X-ray diffraction analyses revealed that active ZnO films demonstrated increased grain size upon annealing from 400 °C to 700 °C, whereas the ZnO film thickness and the annealing of the HfO2 layer in bilayer HfO2/ZnO synaptic devices did not profoundly affect the analog switching behavior. The optimized thermal annealing at 600 °C in bilayer HfO2/ZnO synaptic devices dramatically improved the nonlinearity of long-term potentiation/depression properties, the relative coefficient of variation of the asymmetry distribution σ/µ, and the asymmetry ratio, which approached 1. The results offer valuable insights into the implementation of highly robust synaptic devices in neural networks.

Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET.

Tunneling field-effect transistors (TFETs) are a promising candidate for the next generation of low-power devices, but their performance is very sensitive to traps near the tunneling junction. This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silicon-on-insulator p-type TFET. Without high-pressure annealing, the typical noise power spectral density exhibited two Lorentzian spectra that were affected by fast and slow trap sites. With high-pressure annealing, the interface trap density related to fast trap sites was reduced. The passivation of traps near the tunneling junction indicates that high-pressure H2 and D2 annealing improves the electrical performance and LFN properties, and it may become a significant and necessary step for realizing integrated TFET technology in the future.