A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Application of thermal initiator for characteristic improvements of polymeric replica mold for UV nanoimprint lithography.

We report the improvement of the hardness and modulus properties in a silsesquioxane-based soft replica mold by adding thermal initiator, without deteriorating the UV transmittance at the wavelength of 365 nm. It is found that thermal initiator used for this work contributes to improving the hardness and modulus values up to 0.175 and 3.585 GPa, while the UV transmittance value is still above 75%. The optimized soft replica mold built on a flexible plastic substrate allows submicron-scale patterns to be transferred onto a rigid Si substrate by means of UV-NIL process. Consequently, we demonstrate that the developed soft replica mold can be a suitable replacement for typical hard molds, promising further use in mold-based nanolithography for the fabrication of high-resolution nanopatterns over large areas.

Additive effect of poly(4-vinylphenol) gate dielectric in organic thin film transistor at low temperature process.

We fabricated pentacene-based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics. The solution of gate dielectrics is prepared by adding methylated poly[melamine-co-formaldehyde] (MMF) and photo-initiator (PI) [1-phenyl-2-hydroxy-2-methylpropane-1-one, Darocur1173@Ciba] to PVP By using a small amount (2.4 wt%) of PI, the cross-linking temperature is lowered to 90 degrees C, which is lower than general thermal curing reaction temperature for the cross-linked PVP (> 180 degrees C). The hysteresis and the leakage current of the OTFTs are also decreased by adding the MMF and PI in the PVP gate dielectric.

The effect of thermal annealing on pentacene thin film transistor with micro contact printing.

We used micro contact printing (micro-CP) to fabricate inverted coplanar pentacene thin film transistors (TFTs) with 1-microm channels. The patterning of micro-scale source/drain electrodes without etch process was successfully achieved using Polydimethylsiloxane (PDMS) elastomer stamp. We used the Ag nano particle ink as an electrode material, and the sheet resistance and surface roughness of the Ag electrodes were effectively reduced with the 2-step thermal annealing on a hotplate, which improved the mobility, the on-off ratio, and the subthreshold slope (SS) of the pentacene TFTs. In addition, the device annealing on a hotplate in a N2 atmosphere for 30 sec can enhance the off-current and the mobility properties of OTFTs without damaging the pentacene thin films and increase the adhesion between pentacene and dielectric layer (SiO2), which was investigated with the pentacene films phase change of the XRD spectrum after device annealing.

Formation of metal and dielectric liners using a solution process for deep trench capacitors.

We demonstrated the feasibility of metal and dielectric liners using a solution process for deep trench capacitor application. The deep Si trench via with size of 10.3 microm and depth of 71 microm were fabricated by Bosch process in deep reactive ion etch (DRIE) system. The aspect ratio was about 7. Then, nano-Ag ink and poly(4-vinylphenol) (PVPh) were used to form metal and dielectric liners, respectively. The thicknesses of the Ag and PVPh liners were about 144 and 830 nm, respectively. When the curing temperature of Ag film increased from 120 to 150 degrees C, the sheet resistance decreased rapidly from 2.47 to 0.72 Omega/sq and then slightly decreased to 0.6 Omega/sq with further increasing the curing temperature beyond 150 degrees C. The proposed liner formation method using solution process is a simple and cost effective process for the high capacity of deep trench capacitor.

Effects of seed layer patterns on the structural characteristics of hydrothermally grown ZnO nanorods.

We investigated the effects of surface pattern size and shape on the characteristics of hydrothermally grown ZnO nanorods. For this purpose, the structural characteristics of ZnO nanorods were examined using X-ray diffraction and scanning electron microscopy. The sputtered ZnO seed layer was patterned using photolithography techniques on a Si substrate. ZnO nanorods with a [0001] texturing structure were successfully grown on selective areas by hydrothermal processes. In our experiments, however, it was observed that the diameter and the texture of the ZnO nanorods were strongly influenced by the size of the surface pattern.

Maskless laser direct patterning of PEDOT/PSS layer for soluble process organic thin film transistor.

In this work, we have fabricated TIPS-pentacene TFTs with conductive polymer (3,4-ethylenedioxythiophene):poly(4-stylenesulfonate) (PEDOT:PSS) source/drain electrodes which is patterned by maskless laser direct patterning (LDP). The 5-microm resolution of source and drain patterns with PEDOT:PSS were clearly defined. Furthermore, the OTFTs with 10-microm channel length were successfully achieved by exposing the focused Neodymium:Yttrium Aluminum Garnet (Nd:YAG) laser beam onto the spin-coated PEDOT:PSS films and developing with deionized water. The electrical performance of the TIPS-pentacene TFTs with PEDOT:PSS source/drain electrodes were improved with decrease of the sheet resistance of PEDOT:PSS films when the PEDOT:PSS films were annealed at the temperature above 200 degrees C.

Sub-50 nm template fabrications for nanoimprint lithography using hydrogen silsesquioxane and silicon nitride.

The sub-50 nm templates are successfully fabricated using hydrogen silsesquioxane (HSQ) and silicon nitride on silicon substrate. The HSQ template is directly patterned by e-beam direct writing. The cured HSQ pattern is used for the template of nanoimprint process. The silicon nitride template is reactively ion etched by ZEP resist mask pattern which is prepared by e-beam direct writing using ZEP resist. The line widths of HSQ templates and ZEP patterns after developments are between 22-30 nm and 24-30 nm, respectively. The line width of silicon nitride templates without performing descum is same as that of the ZEP pattern but shows a rough surface. When plasma descum was performed before RIE, the line width of silicon nitride templates increased from 27 nm to 35 nm and has a clean surface. The HSQ template fabrication results in this study will be promise for sub-nm imprint process.