Dust-Sized High-Power-Density Photovoltaic Cells on Si and SOI Substrates for Wafer-Level-Packaged Small Edge Computers.

Advancement in microelectronics technology enables autonomous edge computing platforms in the size of a dust mote (<1 mm), bringing efficient and low-cost artificial intelligence close to the end user and Internet-of-Things (IoT) applications. The key challenge for these compact high-performance edge computers is the integration of a power source that satisfies the high-power-density requirement and does not increase the complexity and cost of the packaging. Here, it is shown that dust-sized III-V photovoltaic (PV) cells grown on Si and silicon-on-insulator (SOI) substrates can be integrated using a wafer-level-packaging process and achieve higher power density than all prior micro-PVs on Si and SOI substrates. The high-throughput heterogeneous integration unlocks the potential of large-scale manufacturing of these integrated systems with low cost for IoT applications. The negative effect of crystallographic defects in the heteroepitaxial materials on PV performance diminishes at high power density. Simultaneous power delivery and data transmission to the dust mote with heteroepitaxially grown PV are also demonstrated using hand-held illumination sources.

Diffusion-Controlled Porous Crystalline Silicon Lithium Metal Batteries.

Nanostructured porous silicon materials have recently advanced as hosts for Li-metal plating. However, limitations involve detrimental silicon self-pulverization, Li-dendrites, and the ability to achieve wafer-level integration of non-composite, pure silicon anodes. compo. Herein, full cells featuring low-resistance, wafer-scale porous crystalline silicon (PCS) anodes are embedded with a nanoporous Li-plating and diffusion-regulating surface layer upon combined wafer surface cleaning (SC) and anodization. LL Lithiophilic surface formation is illustrated via correlation of surface groups and X-ray structure. Low-cost SC-PCS anodes require no composite formulation, and pre-lithiation enables sustainable Li-metal plating/stripping on the lithiophilic surface and in SC-PCS bulk nanostructure. Anodization time and C-rate determined competitive full cell performance: NMC811 | 4800 s SC-PCS: 195 mAh/g (99.9% coulombic efficiency [C.E.], C/3, 50 cycles), 165 mAh/g, 587 Wh/kg (97.1% C.E., C/3 and C/2 rate, 350 cycles), 24 Ω∗cm2 SC-PCS-resistivity (900 cycles); 160 µm LCO | 500 s SC-PCS: 102 mAh/g (94.1% C.E., 1C, 350 cycles).

Single Crystal Flexible Electronics Enabled by 3D Spalling.

Flexible and stretchable electronics are becoming increasingly important in many emerging applications. Due to the outstanding electrical properties of single crystal semiconductors, there is great interest in releasing single crystal thin films and fabricating flexible electronics with these conventionally rigid materials. In this study the authors report a universal single crystal layer release process, called "3D spalling," extending beyond prior art. In contrast to the conventional way of removing blanket layers from their substrates, the new process reported here enables 3D control over the shape and thickness of the removed regions, allowing direct formation of arbitrarily shaped structures of released film and locally specified thickness for each region. As an exemplary demonstration, silicon flexible tactile sensors are fabricated with sensitivities comparable to those of high performance sensors on rigid substrates. Finite element modeling indicates that the size and thickness of the selectively released features can be tuned over a wide range.

Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene.

There are numerous studies on the growth of planar films on sp(2)-bonded two-dimensional (2D) layered materials. However, it has been challenging to grow single-crystalline films on 2D materials due to the extremely low surface energy. Recently, buffer-assisted growth of crystalline films on 2D layered materials has been introduced, but the crystalline quality is not comparable with the films grown on sp(3)-bonded three-dimensional materials. Here we demonstrate direct van der Waals epitaxy of high-quality single-crystalline GaN films on epitaxial graphene with low defectivity and surface roughness comparable with that grown on conventional SiC or sapphire substrates. The GaN film is released and transferred onto arbitrary substrates. The post-released graphene/SiC substrate is reused for multiple growth and transfer cycles of GaN films. We demonstrate fully functional blue light-emitting diodes (LEDs) by growing LED stacks on reused graphene/SiC substrates followed by transfer onto plastic tapes.

Layer-resolved graphene transfer via engineered strain layers.

The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

CMOS-integrated high-speed MSM germanium waveguide photodetector.

A compact waveguide-integrated Germanium-on-insulator (GOI) photodetector with 10 +/- 2fF capacitance and operating at 40Gbps is demonstrated. Monolithic integration of thin single-crystalline Ge into front-end CMOS stack was achieved by rapid melt growth during source-drain implant activation anneal.