Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Tuning the light emission from GaAs nanowires over 290 meV with uniaxial strain.

Strain engineering has been used to increase the charge carrier mobility of complementary metal-oxide-semiconductor transistors as well as to boost and tune the performance of optoelectronic devices, enabling wavelength tuning, polarization selectivity and suppression of temperature drifts. Semiconducting nanowires benefit from enhanced mechanical properties, such as increased yield strength, that turn out to be beneficial to amplify strain effects. Here we use photoluminescence (PL) to study the effect of uniaxial stress on the electronic properties of GaAs/Al0.3Ga0.7As/GaAs core/shell nanowires. Both compressive and tensile mechanical stress were applied continuously and reversibly to the nanowire, resulting in a remarkable decrease of the bandgap of up to 296 meV at 3.5% of strain. Raman spectra were measured and analyzed to determine the axial strain in the nanowire and the Poisson ratio in the <111> direction. In both PL and Raman spectra, we observe fingerprints of symmetry breaking due to anisotropic deformation of the nanowire. The shifts observed in the PL and Raman spectra are well described by bulk deformation potentials for band structure and phonon energies. The fact that exceptionally high elastic strain can be applied to semiconducting nanowires makes them ideally suited for novel device applications that require a tuning of the band structure over a broad range.

In situ doping of catalyst-free InAs nanowires.

We report on in situ doping of InAs nanowires grown by metal-organic vapor-phase epitaxy without any catalyst particles. The effects of various dopant precursors (Si(2)H(6), H(2)S, DETe, CBr(4)) on the nanowire morphology and the axial and radial growth rates are investigated to select dopants that enable control of the conductivity in a broad range and that concomitantly lead to favorable nanowire growth. In addition, the resistivity of individual wires was measured for different gas-phase concentrations of the dopants selected, and the doping density and mobility were extracted. We find that by using Si(2)H(6) axially and radially uniform doping densities up to 7 × 10(19) cm(-3) can be obtained without affecting the morphology or growth rates. For sulfur-doped InAs nanowires, we find that the distribution coefficient depends on the growth conditions, making S doping more difficult to control than Si doping. Moreover, above a critical sulfur gas-phase concentration, compensation takes place, limiting the maximum doping level to 2 × 10(19) cm(-3). Finally, we extract the specific contact resistivity as a function of doping concentration for Ti and Ni contacts.

Silicon nanowire Esaki diodes.

We report on the fabrication and characterization of silicon nanowire tunnel diodes. The silicon nanowires were grown on p-type Si substrates using Au-catalyzed vapor-liquid-solid growth and in situ n-type doping. Electrical measurements reveal Esaki diode characteristics with peak current densities of 3.6 kA/cm(2), peak-to-valley current ratios of up to 4.3, and reverse current densities of up to 300 kA/cm(2) at 0.5 V reverse bias. Strain-dependent current-voltage (I-V) measurements exhibit a decrease of the peak tunnel current with uniaxial tensile stress and an increase of 48% for 1.3 GPa compressive stress along the <111> growth direction, revealing the strain dependence of the Si band structure and thus the tunnel barrier. The contributions of phonons to the indirect tunneling process were probed by conductance measurements at 4.2 K. These measurements show phonon peaks at energies corresponding to the transverse acoustical and transverse optical phonons. In addition, the low-temperature conductance measurements were extended to higher biases to identify potential impurity states in the band gap. The results demonstrate that the most likely impurity, namely, Au from the catalyst particle, is not detectable, a finding that is also supported by the excellent device properties of the Esaki diodes reported here.

Trap-assisted tunneling in Si-InAs nanowire heterojunction tunnel diodes.

We report on the electrical characterization of one-sided p(+)-si/n-InAs nanowire heterojunction tunnel diodes to provide insight into the tunnel process occurring in this highly lattice mismatched material system. The lattice mismatch gives rise to dislocations at the interface as confirmed by electron microscopy. Despite this, a negative differential resistance with peak-to-valley current ratios of up to 2.4 at room temperature and with large current densities is observed, attesting to the very abrupt and high-quality interface. The presence of dislocations and other defects that increase the excess current is evident in the first and second derivative of the I-V characteristics as distinct peaks arising from trap-and phonon-assisted tunneling via the corresponding defect levels. We observe this assisted tunneling mainly in the forward direction and at low reverse bias but not at higher reverse biases because the band-to-band generation rates are peaked in the InAs, which is also confirmed by modeling. This indicates that most of the peaks are due to dislocations and defects in the immediate vicinity of the interface. Finally, we also demonstrate that these devices are very sensitive to electrical stress, in particular at room temperature, because of the extremely high electrical fields obtained at the abrupt junction even at low bias. The electrical stress induces additional defect levels in the band gap, which reduce the peak-to-valley current ratios.

Mapping active dopants in single silicon nanowires using off-axis electron holography.

We demonstrate that state-of-the-art off-axis electron holography can be used to map active dopants in silicon nanowires as thin as 60 nm with 10 nm spatial resolution. Experiment and simulation demonstrate that doping concentrations of 10(19) and 10(20) cm(-3) can be measured with a detection threshold of 10(18) cm(-3) with respect to intrinsic silicon. Comparison of experimental data and simulations allows an estimation of the charge density at the wire-oxide interface of -1 x 10(12) electron charges cm(-2). Off-axis electron holography thus offers unique capabilities for a detailed analysis of active dopant concentrations in nanostructures.

Donor deactivation in silicon nanostructures.

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

Doping limits of grown in situ doped silicon nanowires using phosphine.

Structural characterization and electrical measurements of silicon nanowires (SiNWs) synthesized by Au catalyzed vapor-liquid-solid growth using silane and axially doped in situ with phosphine are reported. We demonstrate that highly n-doped SiNWs can be grown without structural defects and high selectivity and find that addition of the dopant reduces the growth rate by less than 8% irrespective of the radius. This indicates that also the dopant incorporation is radius-independent. On the basis of electrical measurements on individual wires, contact resistivities as low as 1.2 x 10(-7) omega cm(-2) were extracted. Resistivity measurements reveal a reproducible donor incorporation of up to 1.5 x 1020 cm-3 using a gas phase ratios of Si/P = 1.5 x 10(-2). Higher dopant gas concentrations did not lead to an increase of the doping concentration beyond 1.5 x10(20) cm(-3).

Tunable double quantum dots in InAs nanowires defined by local gate electrodes.

We report on low-temperature transport measurements on single and double quantum dots defined using local gates to electrostatically deplete InAs nanowires grown by chemical beam epitaxy. This technique allows us to define multiple quantum dots along a semiconducting nanowire and tune the coupling between them.

Electrical transport through a single nanoscale semiconductor branch point.

Semiconductor tetrapods are three-dimensional (3D) branched nanostructures, representing a new class of materials for electrical conduction. We employ the single-electron transistor approach to investigate how charge carriers migrate through single nanoscale branch points of tetrapods. We find that carriers can delocalize across the branches or localize and hop between arms depending on their coupling strength. In addition, we demonstrate a new single-electron transistor operation scheme enabled by the multiple branched arms of a tetrapod: one arm can be used as a sensitive arm-gate to control the electrical transport through the whole system.