CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning.

Extending Moore's law by augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) has become increasingly important. One important class of problems involve sampling-based Monte Carlo algorithms used in probabilistic machine learning, optimization, and quantum simulation. Here, we combine stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) with Field Programmable Gate Arrays (FPGA) to create an energy-efficient CMOS + X (X = sMTJ) prototype. This setup shows how asynchronously driven CMOS circuits controlled by sMTJs can perform probabilistic inference and learning by leveraging the algorithmic update-order-invariance of Gibbs sampling. We show how the stochasticity of sMTJs can augment low-quality random number generators (RNG). Detailed transistor-level comparisons reveal that sMTJ-based p-bits can replace up to 10,000 CMOS transistors while dissipating two orders of magnitude less energy. Integrated versions of our approach can advance probabilistic computing involving deep Boltzmann machines and other energy-based learning algorithms with extremely high throughput and energy efficiency.

Efficient Probabilistic Computing with Stochastic Perovskite Nickelates.

Probabilistic computing has emerged as a viable approach to solve hard optimization problems. Devices with inherent stochasticity can greatly simplify their implementation in electronic hardware. Here, we demonstrate intrinsic stochastic resistance switching controlled via electric fields in perovskite nickelates doped with hydrogen. The ability of hydrogen ions to reside in various metastable configurations in the lattice leads to a distribution of transport gaps. With experimentally characterized p-bits, a shared-synapse p-bit architecture demonstrates highly parallelized and energy-efficient solutions to optimization problems such as integer factorization and Boolean satisfiability. The results introduce perovskite nickelates as scalable potential candidates for probabilistic computing and showcase the potential of light-element dopants in next-generation correlated semiconductors.

Hardware Design for Autonomous Bayesian Networks.

Directed acyclic graphs or Bayesian networks that are popular in many AI-related sectors for probabilistic inference and causal reasoning can be mapped to probabilistic circuits built out of probabilistic bits (p-bits), analogous to binary stochastic neurons of stochastic artificial neural networks. In order to satisfy standard statistical results, individual p-bits not only need to be updated sequentially but also in order from the parent to the child nodes, necessitating the use of sequencers in software implementations. In this article, we first use SPICE simulations to show that an autonomous hardware Bayesian network can operate correctly without any clocks or sequencers, but only if the individual p-bits are appropriately designed. We then present a simple behavioral model of the autonomous hardware illustrating the essential characteristics needed for correct sequencer-free operation. This model is also benchmarked against SPICE simulations and can be used to simulate large-scale networks. Our results could be useful in the design of hardware accelerators that use energy-efficient building blocks suited for low-level implementations of Bayesian networks. The autonomous massively parallel operation of our proposed stochastic hardware has biological relevance since neural dynamics in brain is also stochastic and autonomous by nature.

Demonstration of a pseudo-magnetization based simultaneous write and read operation in a Co60Fe20B20/Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructure.

Taking advantage of the magnetoelectric and its inverse effect, this article demonstrates strain-mediated magnetoelectric write and read operations simultaneously in Co60Fe20B20/Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructures based on a pseudo-magnetization µ ≡ mx2 - my2. By applying an external DC-voltage across a (011)-cut PMN-PT substrate, the ferroelectric polarization is re-oriented, which results in an anisotropic in-plane strain that transfers to the CoFeB thin film and changes its magnetic anisotropy Hk. The change in Hk in-turn results in a 90° rotation of the magnetic easy axis for sufficiently high voltages. Simultaneously, the inverse effect is employed to read changes of the magnetic properties. The change of magnetization in ferromagnetic (FM) layer induces an elastic stress in the piezoelectric (PE) layer, which generates a PE potential that can be used to readout the magnetic state of the FM layer. The experimental results are in excellent qualitative agreement with an equivalent circuit model that considers how magnetic properties are electrically controlled in such a PE/FM heterostructure and how a back-voltage is generated due to changing magnetic properties in a self-consistent model. We demonstrated that a change of easy axis of magnetization due to an applied voltage can be directly used for information processing, which is essential for future ME based devices.

Probabilistic Circuits for Autonomous Learning: A Simulation Study.

Modern machine learning is based on powerful algorithms running on digital computing platforms and there is great interest in accelerating the learning process and making it more energy efficient. In this paper we present a fully autonomous probabilistic circuit for fast and efficient learning that makes no use of digital computing. Specifically we use SPICE simulations to demonstrate a clockless autonomous circuit where the required synaptic weights are read out in the form of analog voltages. This allows us to demonstrate a circuit that can be built with existing technology to emulate the Boltzmann machine learning algorithm based on gradient optimization of the maximum likelihood function. Such autonomous circuits could be particularly of interest as standalone learning devices in the context of mobile and edge computing.

Integer factorization using stochastic magnetic tunnel junctions.

Conventional computers operate deterministically using strings of zeros and ones called bits to represent information in binary code. Despite the evolution of conventional computers into sophisticated machines, there are many classes of problems that they cannot efficiently address, including inference, invertible logic, sampling and optimization, leading to considerable interest in alternative computing schemes. Quantum computing, which uses qubits to represent a superposition of 0 and 1, is expected to perform these tasks efficiently1-3. However, decoherence and the current requirement for cryogenic operation4, as well as the limited many-body interactions that can be implemented, pose considerable challenges. Probabilistic computing1,5-7 is another unconventional computation scheme that shares similar concepts with quantum computing but is not limited by the above challenges. The key role is played by a probabilistic bit (a p-bit)-a robust, classical entity fluctuating in time between 0 and 1, which interacts with other p-bits in the same system using principles inspired by neural networks8. Here we present a proof-of-concept experiment for probabilistic computing using spintronics technology, and demonstrate integer factorization, an illustrative example of the optimization class of problems addressed by adiabatic9 and gated2 quantum computing. Nanoscale magnetic tunnel junctions showing stochastic behaviour are developed by modifying market-ready magnetoresistive random-access memory technology10,11 and are used to implement three-terminal p-bits that operate at room temperature. The p-bits are electrically connected to form a functional asynchronous network, to which a modified adiabatic quantum computing algorithm that implements three- and four-body interactions is applied. Factorization of integers up to 945 is demonstrated with this rudimentary asynchronous probabilistic computer using eight correlated p-bits, and the results show good agreement with theoretical predictions, thus providing a potentially scalable hardware approach to the difficult problems of optimization and sampling.

Direct observation of valley-coupled topological current in MoS2.

The valley degree of freedom of electrons in two-dimensional transition metal dichalcogenides has been extensively studied by theory (1-4), optical (5-9), and optoelectronic (10-13) experiments. However, generation and detection of pure valley current without relying on optical selection have not yet been demonstrated in these materials. Here, we report that valley current can be electrically induced and detected through the valley Hall effect and inverse valley Hall effect, respectively, in monolayer molybdenum disulfide. We compare temperature and channel length dependence of nonlocal electrical signals in monolayer and multilayer samples to distinguish the valley Hall effect from classical ohmic contributions. Notably, valley transport is observed over a distance of 4 µm in monolayer samples at room temperature. Our findings will enable a new generation of electronic devices using the valley degree of freedom, which can be used for future novel valleytronic applications.

Weighted p -Bits for FPGA Implementation of Probabilistic Circuits.

Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits ( p -bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a "weighted" p -bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p -bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-complete subset sum problem by solving a small instance of this problem in hardware.