Design and fabrication of a microstrip triplexer with wide flat channels for multi-band 5G applications.

In this paper, a new microstrip triplexer is designed to work at 2.5 GHz, 4.4 GHz and 6 GHz for mid-band 5G applications. All channels are flat with three low group delays (GDs) of 0.84 ns, 0.75 ns and 0.49 ns, respectively. Compared to the previously reported works, the proposed triplexer has the minimum group delay. The designed triplexer has 18.2%, 13.7%, 23.6% fractional bandwidths (FBW%) at 2.5 GHz, 4.4 GHz and 6 GHz, respectively. The obtained insertion losses (ILs) are low at all channels. These features are obtained without a noticeable increase in the overall size. A novel and simple resonator is used to design the proposed triplexer, which includes two pairs of coupled lines combined with a shunt stub. A perfect mathematical analysis is performed to find the resonator behavior and the layout optimization. The type of shunt stub is determined mathematically. Also, the smallness or largeness of some important physical dimensions is determined using the proposed mathematical analysis. Finally, the designed triplexer is fabricated and measured, where the measurement results verify the simulations.

Designing process and analysis of a new SOI-MESFET structure with enhanced DC and RF characteristics for high-frequency and high-power applications.

This research introduces a new designing process and analysis of an innovative Silicon-on-Insulator Metal-Semiconductor Field-Effect (SOI MESFET) structure that demonstrates improved DC and RF characteristics. The design incorporates several modifications to control and reduce the electric field concentration within the channel. These modifications include relocating the transistor channel to sub-regions near the source and drain, adjusting the position of the gate electrode closer to the source, introducing an aluminum layer beneath the channel, and integrating an oxide layer adjacent to the gate. The results show that the AlOx-MESFET configuration exhibits a remarkable increase of 128% in breakdown voltage and 156% in peak power. Furthermore, due to enhanced conductivity and a significant reduction in gate-drain capacitance, there is a notable improvement of 53% in the cut-off frequency and a 28% increase in the maximum oscillation frequency. Additionally, the current gain experiences a boost of 15%. The improved breakdown voltage and peak power make it suitable for applications requiring robust performance under high voltage and power conditions. The increased maximum oscillation frequency and cut-off frequency make it ideal for high-frequency applications where fast signal processing is crucial. Moreover, the enhanced current gain ensures efficient amplification of signals. The introduced SOI MESFET structure with its modifications offers significant improvements in various performance metrics. It provides high oscillation frequency, better breakdown voltage and good cut-off frequency, and current gain compared to the traditional designs. These enhancements make it a highly desirable choice for applications that demand high-frequency and high-power capabilities.

Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.

The development of prostheses and treatments for illnesses and recovery has recently been centered on hardware modeling for various delicate biological components, including the nervous system, brain, eyes, and heart. The retina, being the thinnest and deepest layer of the eye, is of particular interest. In this study, we employ the Nyquist-Based Approximation of Retina Rod Cell (NBAoRRC) approach, which has been adapted to utilize Look-Up Tables (LUTs) rather than original functions, to implement rod cells in the retina using cost-effective hardware. In modern mathematical models, numerous nonlinear functions are used to represent the activity of these cells. However, these nonlinear functions would require a substantial amount of hardware for direct implementation and may not meet the required speed constraints. The proposed method eliminates the need for multiplication functions and utilizes a fast, cost-effective rod cell device. Simulation results demonstrate the extent to which the proposed model aligns with the behavior of the primary rod cell model, particularly in terms of dynamic behavior. Based on the results of hardware implementation using the Field-Programmable Gate Arrays (FPGA) board Virtex-5, the proposed model is shown to be reliable, consume 30 percent less power than the primary model, and have reduced hardware resource requirements. Based on the results of hardware implementation using the reconfigurable FPGA board Virtex-5, the proposed model is reliable, uses 30% less power consumption than the primary model in the worth state of the set of approximation method, and has a reduced hardware resource requirement. In fact, using the proposed model, this reduction in the power consumption can be achieved. Finally, in this article, by using the LUT which is systematically sampled (Nyquist rate), we were able to remove all costly operators in terms of hardware (digital) realization and achieve very good results in the field of digital implementation in two scales of network and single neuron.

A new compact and low phase imbalance microstrip coupler for 5G wireless communication systems.

Microstrip couplers play a crucial role in signal processing and transmission in various applications, including RF and wireless communication, radar systems, and satellites. In this work, a novel microstrip 180° coupler is designed, fabricated and measured. The layout configuration of this coupler is completely new and different from the previously reported Rat-race, branch-line and directional couplers. To obtain the proposed coupler, the meandrous coupled lines are used and analyzed mathematically. To improve the performance of our coupler, an optimization method is used. The designed coupler is very compact with an overall size of 0.014λg2. The obtained values of S21 and S31 are -3.45 dB and -3.75 dB, respectively at the operating frequency, while the fractional bandwidth (FBW) is 56.2%. It operates at fo = 1.61 GHz (suitable for 5G applications) and can suppress harmonics up to 2.17fo. Another advantage of this coupler is its low phase imbalance, while the phase difference between S21 and S31 is 180°± 0.023°. Therefore, our device is a balanced coupler with ±0.3 dB magnitude unbalance at its operating frequency. It is important to note that it is very difficult to find a coupler that has all these advantages at the same time. The proposed 180° coupler is fabricated and measured. The comparison shows that the measurement and simulation results are in good agreement. Therefore, the proposed coupler can be easily used in designing high-performance 5G communication systems.

Mutual Coupling Reduction in Antenna Arrays Using Artificial Intelligence Approach and Inverse Neural Network Surrogates.

This paper presents a novel approach to reducing undesirable coupling in antenna arrays using custom-designed resonators and inverse surrogate modeling. To illustrate the concept, two standard patch antenna cells with 0.07λ edge-to-edge distance were designed and fabricated to operate at 2.45 GHz. A stepped-impedance resonator was applied between the antennas to suppress their mutual coupling. For the first time, the optimum values of the resonator geometry parameters were obtained using the proposed inverse artificial neural network (ANN) model, constructed from the sampled EM-simulation data of the system, and trained using the particle swarm optimization (PSO) algorithm. The inverse ANN surrogate directly yields the optimum resonator dimensions based on the target values of its S-parameters being the input parameters of the model. The involvement of surrogate modeling also contributes to the acceleration of the design process, as the array does not need to undergo direct EM-driven optimization. The obtained results indicate a remarkable cancellation of the surface currents between two antennas at their operating frequency, which translates into isolation as high as -46.2 dB at 2.45 GHz, corresponding to over 37 dB improvement as compared to the conventional setup.

A Compact Rat-Race Coupler with Harmonic Suppression for GSM Applications: Design and Implementation Using Artificial Neural Network.

In this paper, a compact microstrip rat-race coupler at a 950 MHz operating frequency is designed, simulated, and fabricated. New branches are proposed in this design using high-/low- impedance open-ended resonators. In the conventional rat-race coupler, there are three long λ/4 branches and a 3λ/4 branch, and they occupy a very large area. In the presented designed, three compact branches are proposed for use instead of three λ/4 branches and an ultra-compact branch is suggested for use instead of the 3λ/4 branch. Additionally, an artificial neural network (ANN) approach is incorporated to improve the performance of the resonators using a radial basis function (RBF) network. The proposed compact structure has achieved a reduction of more than 82% compared with the size of the conventional coupler structures. Additionally, the proposed coupler can suppress the 2nd up to the 5th harmonic to improve the performance of the device.

A Miniaturized Dual-Band Diplexer Design with High Port Isolation for UHF/SHF Applications Using a Neural Network Model.

In this paper, a compact dual-band diplexer is proposed using two interdigital filters. The proposed microstrip diplexer correctly works at 2.1 GHz and 5.1 GHz. In the proposed diplexer, two fifth-order bandpass interdigital filters are designed to pass the desired frequency bands. Applied interdigital filters with simple structures pass the 2.1 GHz and 5.1 GHz frequencies and suppress other frequency bands with high attenuation levels. The dimensions of the interdigital filter are obtained using the artificial neural network (ANN) model, constructed from the EM-simulation data. The desired filter and diplexer parameters, such as operating frequency, bandwidth, and insertion loss, can be obtained using the proposed ANN model. The insertion loss parameter of the proposed diplexer is 0.4 dB, and more than 40 dB output port isolation is obtained (for both operating frequencies). The main circuit has the small size of 28.5 mm × 23 mm (0.32 λg × 0.26 λg). The proposed diplexer, with the achieved desired parameters, is a good candidate for UHF/SHF applications.

A Super-Efficient GSM Triplexer for 5G-Enabled IoT in Sustainable Smart Grid Edge Computing and the Metaverse.

Global concerns regarding environmental preservation and energy sustainability have emerged due to the various impacts of constantly increasing energy demands and climate changes. With advancements in smart grid, edge computing, and Metaverse-based technologies, it has become apparent that conventional private power networks are insufficient to meet the demanding requirements of industrial applications. The unique capabilities of 5G, such as numerous connections, high reliability, low latency, and large bandwidth, make it an excellent choice for smart grid services. The 5G network industry will heavily rely on the Internet of Things (IoT) to progress, which will act as a catalyst for the development of the future smart grid. This comprehensive platform will not only include communication infrastructure for smart grid edge computing, but also Metaverse platforms. Therefore, optimizing the IoT is crucial to achieve a sustainable edge computing network. This paper presents the design, fabrication, and evaluation of a super-efficient GSM triplexer for 5G-enabled IoT in sustainable smart grid edge computing and the Metaverse. This component is intended to operate at 0.815/1.58/2.65 GHz for 5G applications. The physical layout of our triplexer is new, and it is presented for the first time in this work. The overall size of our triplexer is only 0.007 λg2, which is the smallest compared to the previous works. The proposed triplexer has very low insertion losses of 0.12 dB, 0.09 dB, and 0.42 dB at the first, second, and third channels, respectively. We achieved the minimum insertion losses compared to previous triplexers. Additionally, the common port return losses (RLs) were better than 26 dB at all channels.

Design of a Compact Quad-Channel Microstrip Diplexer for L and S Band Applications.

In this paper, two novel dual-band bandpass filters (BPFs) and a compact quad-channel diplexer working at 1.7/3.3 GHz and 1.9/3.6 GHz are proposed. In the proposed diplexer design, triangular loop resonators and rectangular loop resonators are used together to reduce the circuit size and improve diplexer performances. Insertion loss (IL) and return loss (RL) of the proposed diplexer are better than 0.8 dB and 21 dB, respectively, at these four operating frequencies. Output ports isolation parameter is better than 30 dB. With the achieved specifications, the proposed diplexer can be used in L and S band applications.

SELAMAT: A New Secure and Lightweight Multi-Factor Authentication Scheme for Cross-Platform Industrial IoT Systems.

The development of the industrial Internet of Things (IIoT) promotes the integration of the cross-platform systems in fog computing, which enable users to obtain access to multiple application located in different geographical locations. Fog users at the network's edge communicate with many fog servers in different fogs and newly joined servers that they had never contacted before. This communication complexity brings enormous security challenges and potential vulnerability to malicious threats. The attacker may replace the edge device with a fake one and authenticate it as a legitimate device. Therefore, to prevent unauthorized users from accessing fog servers, we propose a new secure and lightweight multi-factor authentication scheme for cross-platform IoT systems (SELAMAT). The proposed scheme extends the Kerberos workflow and utilizes the AES-ECC algorithm for efficient encryption keys management and secure communication between the edge nodes and fog node servers to establish secure mutual authentication. The scheme was tested for its security analysis using the formal security verification under the widely accepted AVISPA tool. We proved our scheme using Burrows Abdi Needham's logic (BAN logic) to prove secure mutual authentication. The results show that the SELAMAT scheme provides better security, functionality, communication, and computation cost than the existing schemes.