Wafer-scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium.

The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation. Furthermore, the weak interaction between graphene and underlying hydrogen-terminated germanium surface enabled the facile etch-free dry transfer of graphene and the recycling of the germanium substrate for continual graphene growth.

Reliability enhancement of germanium nanowires using graphene as a protective layer: aspect of thermal stability.

We synthesized thermally stable graphene-covered Ge (Ge@G) nanowires and applied them in field emission devices. Vertically aligned Ge@G nanowires were prepared by sequential growth of the Ge nanowires and graphene shells in a single chamber. As a result of the thermal treatment experiments, Ge@G nanowires were much more stable than pure Ge nanowires, maintaining their shape at high temperatures up to 850 °C. In addition, field emission devices based on the Ge@G nanowires clearly exhibited enhanced thermal reliability. Moreover, field emission characteristics yielded the highest field enhancement factor (∼2298) yet reported for this type of device, and also had low turn-on voltage. Our proposed approach for the application of graphene as a protective layer for a semiconductor nanowire is an efficient way to enhance the thermal reliability of nanomaterials.

Large-scale fabrication of 2-D nanoporous graphene using a thin anodic aluminum oxide etching mask.

A large-scale nanoporous graphene (NPG) fabrication method via a thin anodic aluminum oxide (AAO) etching mask is presented in this paper. A thin AAO film is successfully transferred onto a hydrophobic graphene surface under no external force. The AAO film is completely stacked on the graphene due to the van der Waals force. The neck width of the NPG can be controlled ranging from 10 nm to 30 nm with different AAO pore widening times. Extension of the NPG structure is demonstrated on a centimeter scale up to 2 cm2. AAO and NPG structures are characterized using optical microscopy (OM), Raman spectroscopy and field-emission scanning electron microscopy (FE-SEM). A field effect transistor (FET) is realized by using NPG. Its electrical characteristics turn out to be different from that of pristine graphene, which is due to the periodic nanostructures. The proposed fabrication method could be adapted to a future graphene-based nano device.

A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope.

We present a facile CMOS-compatible fabrication of lateral gate-all-around (GAA) field effect transistors (FETs) based on concentric Si-SiO2/N(++)Si core-multi-shell nanowires (NWs). Si-SiO2/N(++)Si core-multi-shell NWs were prepared by sequential Si NW growth, thermal oxidation and Si deposition processes in a single chamber. The GAA NW FET was then fabricated using the Si core, SiO2 inner-shell, N(++) Si outer-shell as a channel, gate dielectric, and gate electrode, respectively. A one-step wet etching process was able to define the gate and source-drain contact regions. The SiNW GAA FET clearly exhibits a geometry-dependent gating effect and a steep subthreshold slope due to the low interface trapped charge density at the interface of the Si core and the SiO2 shell. Our proposed SiNW GAA structures offer new opportunities for low-energy-consumption digital device applications.