Intrinsically ultrastrong plasmon-exciton interactions in crystallized films of carbon nanotubes.

In cavity quantum electrodynamics, optical emitters that are strongly coupled to cavities give rise to polaritons with characteristics of both the emitters and the cavity excitations. We show that carbon nanotubes can be crystallized into chip-scale, two-dimensionally ordered films and that this material enables intrinsically ultrastrong emitter-cavity interactions: Rather than interacting with external cavities, nanotube excitons couple to the near-infrared plasmon resonances of the nanotubes themselves. Our polycrystalline nanotube films have a hexagonal crystal structure, ∼25-nm domains, and a 1.74-nm lattice constant. With this extremely high nanotube density and nearly ideal plasmon-exciton spatial overlap, plasmon-exciton coupling strengths reach 0.5 eV, which is 75% of the bare exciton energy and a near record for room-temperature ultrastrong coupling. Crystallized nanotube films represent a milestone in nanomaterials assembly and provide a compelling foundation for high-ampacity conductors, low-power optical switches, and tunable optical antennas.

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules.

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

First realization of the piezoelectronic stress-based transduction device.

We present the first realization of a monolithically integrated piezoelectronic transistor (PET), a new transduction-based computer switch which could potentially operate conventional computer logic at 1/50 the power requirements of current Si-based transistors (Chen 2014 Proc. IEEE ICICDT pp 1-4; Mamaluy et al 2014 Proc. IWCE pp 1-2). In PET operation, an input gate voltage expands a piezoelectric element (PE), transducing the input into a pressure pulse which compresses a piezoresistive element (PR). The PR resistance goes down, transducing the signal back to voltage and turning the switch 'on'. This transduction physics, in principle, allows fast, low-voltage operation. In this work, we address the processing challenges of integrating chemically incompatible PR and PE materials together within a surrounding cage against which the PR can be compressed. This proof-of-concept demonstration of a fully integrated, stand-alone PET device is a key step in the development path toward a fast, low-power very large scale integration technology.

Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Multiple double cross-section transmission electron microscope sample preparation of specific sub-10 nm diameter Si nanowire devices.

The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dual-beam focused ion beam system in a direction running parallel to the device channel. From this XTEM sample, both low- and high-resolution transmission electron microscope (TEM) images were obtained from six separate, specific site Si NW devices. The XTEM sample was then re-sectioned in four separate locations in a direction perpendicular to the device channel: 90° from the original XTEM sample direction. Three of the four XTEM samples were successfully sectioned in the gate region of the device. From these three samples, low- and high-resolution TEM images of the Si NW were taken and measurements of the NW diameters were obtained. This technique demonstrated the ability to obtain high-resolution TEM images in directions 90° from one another of multiple, specific sub-10 nm features that were spaced 1.1 µm apart.

Three-dimensional measurement of line edge roughness in copper wires using electron tomography.

Electrical interconnects in integrated circuits have shrunk to sizes in the range of 20-100 nm. Accurate measurements of the dimensions of these nanowires are essential for identifying the dominant electron scattering mechanisms affecting wire resistivity as they continue to shrink. We report a systematic study of the effect of line edge roughness on the apparent cross-sectional area of 90 nm Cu wires with a TaN/Ta barrier measured by conventional two-dimensional projection imaging and three-dimensional electron tomography. Discrepancies in area measurements due to the overlap of defects along the wire's length lead to a 5% difference in the resistivities predicted by the two methods. Tomography of thick cross sections is shown to give a more accurate representation of the original structure and allows more efficient sampling of the wire's cross-sectional area. The effect of roughness on measurements from projection images is minimized for cross-section thicknesses less than 50 nm, or approximately half the spatial frequency of the roughness variations along the length of the investigated wires.