Influence of uterine manipulator use on the incidence of lymphovascular propagation in the treatment of endometrial cancer.

BACKGROUND: Endometrial cancers are among the epithelial malignancies of the lining of the uterine cavity. The invasion of carcinoma into the lymphovascular space (LVSI) is considered a risk factor for the course of the disease. MATERIAL AND METHODS: We evaluated 170 female patients. Our primary objective was to find any difference in the incidence of LVSI in female patients treated with and without an intrauterine manipulator. In addition, we analyzed the effect of the type of intrauterine manipulator used on the incidence of LVSI, tumor grading, myometrial invasion, and the method of obtaining primary histology with regard to the incidence of LVSI. RESULTS: Using a manipulator during surgery was not associated with LVSI (with a manipulator vs. without, 11.5 vs. 21.7%; OR 1.8; 95% CI 0.73-4.39; p = 0.199). However, the method used to obtain the primary histology had a statistically significant effect on the incidence of LVSI in our set (p-value = 0.011). CONCLUSIONS: In our study, we did not confirm the effect of a uterine manipulator on the possible increase of LVSI positive cases. The secondary analysis indicated a higher incidence of LVSI in the female patients diagnosed with curettage than in those who underwent hysteroscopy. Trail registration: Trail is registered in ClicincalTrails.gov with identifier: NCT05261165.

Additive Manufacturing in Atomic Layer Processing Mode.

Additive manufacturing (3D printing) has not been applicable to micro- and nanoscale engineering due to the limited resolution. Atomic layer deposition (ALD) is a technique for coating large areas with atomic thickness resolution based on tailored surface chemical reactions. Thus, combining the principles of additive manufacturing with ALD could open up a completely new field of manufacturing. Indeed, it is shown that a spatially localized delivery of ALD precursors can generate materials patterns. In this "atomic-layer additive manufacturing" (ALAM), the vertical resolution of the solid structure deposited is about 0.1 nm, whereas the lateral resolution is defined by the microfluidic gas delivery. The ALAM principle is demonstrated by generating lines and patterns of pure, crystalline TiO2 and Pt on planar substrates and conformal coatings of 3D nanostructures. The functional quality of ALAM patterns is exemplified with temperature sensors, which achieve a performance similar to the industry standard. This general method of multimaterial direct patterning is much simpler than standard multistep lithographic microfabrication. It offers process flexibility, saves processing time, investment, materials, waste, and energy. It is envisioned that together with etching, doping, and cleaning performed in a similar local manner, ALAM will create the "atomic-layer advanced manufacturing" family of techniques.

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.

von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistor.

Carrier transport in layered transition-metal dichalcogenides is highly sensitive to surrounding charges because of the atomically thin thickness. By exploiting this property, we report a new internal current amplification mechanism through positive feedback induced by dielectric hole trapping in a MoS2 back-gate transistor on a tantalum oxide substrate. The device exhibits an extremely steep subthreshold slope of 17 mV/decade, which is strongly dependent on the substrate material and drain bias. The steep subthreshold slope is attributed to the internal current amplification arising from the positive feedback between hole generation in MoS2 triggered by large lateral electric field and Schottky barrier narrowing induced by localized hole trapping in tantalum oxide near the source contact.

Nanoscale characterization of TiO(2) films grown by atomic layer deposition on RuO(2) electrodes.

Topography and leakage current maps of TiO2 films grown by atomic layer deposition on RuO2 electrodes using either a TiCl4 or a Ti(O-i-C3H7)4 precursor were characterized at nanoscale by conductive atomic force microscopy (CAFM). For both films, the leakage current flows mainly through elevated grains and not along grain boundaries. The overall CAFM leakage current is larger and more localized for the TiCl4-based films (0.63 nm capacitance equivalent oxide thickness, CET) compared to the Ti(O-i-C3H7)4-based films (0.68 nm CET). Both films have a physical thickness of ∼20 nm. The nanoscale leakage currents are consistent with macroscopic leakage currents from capacitor structures and are correlated with grain characteristics observed by topography maps and transmission electron microscopy as well as with X-ray diffraction.