Barrier Height, Ideality Factor and Role of Inhomogeneities at the AlGaN/GaN Interface in GaN Nanowire Wrap-Gate Transistor.

It is essential to understand the barrier height, ideality factor, and role of inhomogeneities at the metal/semiconductor interfaces in nanowires for the development of next generation nanoscale devices. Here, we investigate the drain current (Ids)-gate voltage (Vgs) characteristics of GaN nanowire wrap-gate transistors (WGTs) for various gate potentials in the wide temperature range of 130-310 K. An anomalous reduction in the experimental barrier height and rise in the ideality factor with reducing the temperature have been perceived. It is noteworthy that the variations in barrier height and ideality factor are attributed to the spatial barrier inhomogeneities at the AlGaN/GaN interface in the GaN nanowire WGTs by assuming a double Gaussian distribution of barrier heights at 310-190 K (distribution 1) and 190-130 K (distribution 2). The standard deviation for distribution 2 is lower than that of distribution 1, which suggests that distribution 2 reflects more homogeneity at the AlGaN/GaN interface in the transistor's source/drain regions than distribution 1.

Carrier Trap and Their Effects on the Surface and Core of AlGaN/GaN Nanowire Wrap-Gate Transistor.

We used capacitance-voltage (C-V), conductance-voltage (G-V), and noise measurements to examine the carrier trap mechanisms at the surface/core of an AlGaN/GaN nanowire wrap-gate transistor (WGT). When the frequency is increased, the predicted surface trap density promptly drops, with values ranging from 9.1 × 1013 eV-1∙cm-2 at 1 kHz to 1.2 × 1011 eV-1∙cm-2 at 1 MHz. The power spectral density exhibits 1/f-noise behavior in the barrier accumulation area and rises with gate bias, according to the 1/f-noise features. At lower frequencies, the device exhibits 1/f-noise behavior, while beyond 1 kHz, it exhibits 1/f2-noise behavior. Additionally, when the fabricated device governs in the deep-subthreshold regime, the cutoff frequency for the 1/f2-noise features moves to the subordinated frequency (~102 Hz) side.

Temperature-Dependent Carrier Transport in GaN Nanowire Wrap-Gate Transistor.

For the creation of next-generation nanoscale devices, it is crucial to comprehend the carrier transport mechanisms in nanowires. Here, we examine how temperature affects the properties of GaN nanowire wrap-gate transistors (WGTs), which are made via a top-down technique. The predicted conductance in this transistor remains essentially unaltered up to a temperature of 240 K and then increases after that as the temperature rises. This is true for increasing temperature at gate voltages less than threshold voltage (Vgs < Vth). Sharp fluctuations happen when the temperature rises with a gate voltage of Vth < Vgs < VFB. The conductance steadily decreases with increasing temperature after increasing the gate bias to Vgs > VFB. These phenomena are possibly attributed to phonon and impurity scattering processes occurring on the surface or core of GaN nanowires.

Viscosity-Controllable Graphene Oxide Colloids Using Electrophoretically Deposited Graphene Oxide Sheets.

Graphene oxide (GO) is one of the interesting ink materials owing to its fascinating properties, such as high dissolubility in water and high controllable electric properties. For versatile printing application, the viscosity of GO colloids should be controlled in order to meet the specific process requirements. Here, we report on the relatively rapid fabrication of viscosity-increased GO (VIGO) colloids mixed with electrophoretically deposited GO sheets (EPD-GO). As the GO colloid concentration, applied voltage, and deposition time increase, the viscosity of the GO colloids becomes high. The reason for the improved viscosity of GO colloids is because EPD-GO has parallel stacked GO sheets. The GO and VIGO colloids are compared and characterized using various chemical and structural analyzers. Consequently, our simple and fast method for the fabrication of GO colloids with enhanced viscosity can be used for producing inks for flexible and printed electronics.

Low-Frequency Noise Characteristics in HfO2-Based Metal-Ferroelectric-Metal Capacitors.

The transport mechanism of HfO2-based metal-ferroelectric-metal (MFM) capacitors was investigated using low-frequency noise (LFN) measurements for the first time. The current-voltage measurement results revealed that the leakage behavior of the fabricated MFM capacitor was caused by the trap-related Poole-Frenkel transport mechanism, which was confirmed by the LFN measurements. The current noise power spectral densities (SI) obtained from the LFN measurements followed 1/f noise shapes and exhibited a constant electric field (E) × SI/I2 noise behavior. No polarization dependency was observed in the transport characteristics of the MFM capacitor owing to its structural symmetry.

High Device Performances and Noise Characteristics of AlGaN/GaN HEMTs Using In Situ SiCN and SiN Cap Layer.

We fabricated and characterized AlGaN/GaN high-electron mobility transistors (HEMTs) with a nano-sized in situ cap layer (one is a silicon carbon nitride (SiCN) layer, and the other is a silicon nitride (SiN) layer) comparing to the conventional device without an in situ cap layer. The pulse characteristics and noise behaviors for two devices with in situ cap layers are much superior to those of the reference device without a cap layer, which means that the in situ cap layer effectively passivates the AlGaN surface. On the other hand, the device with an in situ SiCN cap layer showed the excellent device characteristics and noise performances compared to the other devices because of the reduced positive ionic charges and enhanced surface morphology caused by carbon (C) surfactant atoms during the growth of the SiCN cap layer. These results indicate that the AlGaN/GaN HEMT with the in situ SiCN cap layer is very promising for the next high-power device by replacing the conventional HEMT.

Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors.

We investigate the DC, C-V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel. From I-V and C-V curves, the fabricated GaN nanowire GAA transistor with AlGaN layer clearly exhibits normally-on operation with negative threshold voltage (Vth) due to the existence of 2DEG channel on the trapezoidal shaped GaN nanowire. On the other hand, the GaN nanowire GAA transistor without AlGaN layer presents a positive Vth (normally-off operation) due to the absent of 2DEG channel on the triangle shaped GaN nanowire. However, both devices show the similar temperaturedependent I-V characteristics due to the combination of bulk channel and surface channel in GaN nanowire GAA channel are mostly contributed, rather than the 2DEG channel. GaN-based nanowire GAA transistors demonstrate to almost negligible current collapse phenomenon due to the perfect GAA gate structure in GaN nanowire. The proposed GaN-based nanowire GAA transistors are very promising candidate for both high power device and nano-electronics application.

Performance of AlGaN/GaN Nanowire Omega-Shaped-Gate Fin-Shaped Field-Effect Transistor.

The AlGaN/GaN nanowire omega-shaped-gate FinFET have been successfully fabricated demonstrating much improved performance compared to conventional AlGaN/GaN MISHFET. The AlGaN/GaN omega-shaped-gate FinFET exhibited the remarkable on-state performances, such as maximum drain current of 1.1 A/mm, low on-resistance, and low current collapse compared to that of the conventional device structure. In addition, the excellent off-state performances were measured: low off-state leakage current as low as -10(-10) mA, the theoretical SS value of -62 mV/dec, and high I(ON)/I(OFF) ratio (-10(9)). Improved dc performances were obtained for omega-shaped-gate structure due to the fully depletion of the active fin body and perfectly separation of the depleted fin from the underlying thick GaN buffer layer. Furthermore, the additional reason for the enhanced device performance of the proposed device is the improved gate controllability compared to the conventional MISHFET. The proposed nano-structure device is very promising candidate for the steep switching device applications.