Metrology for the next generation of semiconductor devices.

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

Post-directed-self-assembly membrane fabrication for in situ analysis of block copolymer structures.

Full characterization of the three-dimensional structures resulting from the directed self-assembly (DSA) of block copolymers (BCP) remains a difficult challenge. Transmission electron microscope (TEM) tomography and resonant soft x-ray scattering have emerged as powerful and complementary methods for through-film characterization; both techniques require samples to be prepared on specialized membrane substrates. Here we report a generalizable process to implement BCP DSA with density multiplication on silicon nitride membranes. A key feature of the process developed here is that it does not introduce any artefacts or damage to the polymer assemblies as DSA is performed prior to back-etched membrane formation. Because most research and applications of BCP lithography are based on silicon substrates, process variations introduced by implementing DSA on a silicon nitride/silicon stack versus silicon were identified and mitigated. Using full-wafers, membranes were fabricated with different sizes and layouts to enable both TEM and x-ray characterization. Finally, both techniques were used to characterize structures resulting from the DSA of lamella-forming BCP with density multiplication.

Scanning electron microscope measurement of width and shape of 10nm patterned lines using a JMONSEL-modeled library.

The width and shape of 10nm to 12 nm wide lithographically patterned SiO2 lines were measured in the scanning electron microscope by fitting the measured intensity vs. position to a physics-based model in which the lines' widths and shapes are parameters. The approximately 32 nm pitch sample was patterned at Intel using a state-of-the-art pitch quartering process. Their narrow widths and asymmetrical shapes are representative of near-future generation transistor gates. These pose a challenge: the narrowness because electrons landing near one edge may scatter out of the other, so that the intensity profile at each edge becomes width-dependent, and the asymmetry because the shape requires more parameters to describe and measure. Modeling was performed by JMONSEL (Java Monte Carlo Simulation of Secondary Electrons), which produces a predicted yield vs. position for a given sample shape and composition. The simulator produces a library of predicted profiles for varying sample geometry. Shape parameter values are adjusted until interpolation of the library with those values best matches the measured image. Profiles thereby determined agreed with those determined by transmission electron microscopy and critical dimension small-angle x-ray scattering to better than 1 nm.

Contact-induced crystallinity for high-performance soluble acene-based transistors and circuits.

The use of organic materials presents a tremendous opportunity to significantly impact the functionality and pervasiveness of large-area electronics. Commercialization of this technology requires reduction in manufacturing costs by exploiting inexpensive low-temperature deposition and patterning techniques, which typically lead to lower device performance. We report a low-cost approach to control the microstructure of solution-cast acene-based organic thin films through modification of interfacial chemistry. Chemically and selectively tailoring the source/drain contact interface is a novel route to initiating the crystallization of soluble organic semiconductors, leading to the growth on opposing contacts of crystalline films that extend into the transistor channel. This selective crystallization enables us to fabricate high-performance organic thin-film transistors and circuits, and to deterministically study the influence of the microstructure on the device characteristics. By connecting device fabrication to molecular design, we demonstrate that rapid film processing under ambient room conditions and high performance are not mutually exclusive.