Effect of Ionic Strength, Nanoparticle Surface Charge Density, and Template Diameter on Self-Limiting Single-Particle Placement: A Numerical Study.

For the bottom-up approach where functional materials are constructed out of nanoscale building blocks (e.g., nanoparticles), it is essential to have methods that are capable of placing the individual nanoscale building blocks onto exact substrate positions on a large scale and on a large area. One of the promising placement methods is the self-limiting single-particle placement (SPP), in which a single nanoparticle in a colloidal solution is electrostatically guided by electrostatic templates and exactly one single nanoparticle is placed on each target position in a self-limiting way. This paper presents a numerical study on SPP, where the effects of three key parameters, (1) ionic strength (IS), (2) nanoparticle surface charge density (σNP), and (3) circular template diameter (d), on SPP are investigated. For 40 different parameter sets of (IS, σNP, d), a 30 nm nanoparticle positioned at R⃗ above the substrate was modeled in two configurations (i) without and (ii) with the presence of a 30 nm nanoparticle at the center of a circular template. For each parameter set and each configuration, the electrostatic potentials were calculated by numerically solving the Poisson-Boltzmann equation, from which interaction forces and interaction free energies were subsequently calculated. These have identified realms of parameter sets that enable a successful SPP. A few exemplary parameter sets include (IS, σNP, d) = (0.5 mM, -1.5 µC/cm2, 100 nm), (0.05 mM, -0.5 µC/cm2, 100 nm), (0.5 mM, -1.5 µC/cm2, 150 nm), and (0.05 mM, -0.8 µC/cm2, 150 nm). This study provides clear guidance toward experimental realizations of large-scale and large-area SPPs, which could lead to bottom-up fabrications of novel electronic, photonic, plasmonic, and spintronic devices and sensors.

Energy-filtered cold electron transport at room temperature.

Fermi-Dirac electron thermal excitation is an intrinsic phenomenon that limits functionality of various electron systems. Efforts to manipulate electron thermal excitation have been successful when the entire system is cooled to cryogenic temperatures, typically <1 K. Here we show that electron thermal excitation can be effectively suppressed at room temperature, and energy-suppressed electrons, whose energy distribution corresponds to an effective electron temperature of ~45 K, can be transported throughout device components without external cooling. This is accomplished using a discrete level of a quantum well, which filters out thermally excited electrons and permits only energy-suppressed electrons to participate in electron transport. The quantum well (~2 nm of Cr2O3) is formed between source (Cr) and tunnelling barrier (SiO2) in a double-barrier-tunnelling-junction structure having a quantum dot as the central island. Cold electron transport is detected from extremely narrow differential conductance peaks in electron tunnelling through CdSe quantum dots, with full widths at half maximum of only ~15 mV at room temperature.

CMOS-compatible fabrication of room-temperature single-electron devices.

Devices in which the transport and storage of single electrons are systematically controlled could lead to a new generation of nanoscale devices and sensors. The attractive features of these devices include operation at extremely low power, scalability to the sub-nanometre regime and extremely high charge sensitivity. However, the fabrication of single-electron devices requires nanoscale geometrical control, which has limited their fabrication to small numbers of devices at a time, significantly restricting their implementation in practical devices. Here we report the parallel fabrication of single-electron devices, which results in multiple, individually addressable, single-electron devices that operate at room temperature. This was made possible using CMOS fabrication technology and implementing self-alignment of the source and drain electrodes, which are vertically separated by thin dielectric films. We demonstrate clear Coulomb staircase/blockade and Coulomb oscillations at room temperature and also at low temperatures.

Electrostatic funneling for precise nanoparticle placement: a route to wafer-scale integration.

We demonstrate a large-scale placement of nanoparticles through a scheme named "electrostatic funneling", in which charged nanoparticles are guided by an electrostatic potential energy gradient and placed on targeted locations with nanoscale precision. The guiding electrostatic structures are defined using current CMOS fabrication technology. The effectiveness of this scheme is demonstrated for a variety of geometries including one-dimensional and zero-dimensional patterns as well as three-dimensional step structures. Placement precision of 6 nm has been demonstrated using a one-dimensional guiding structure comprising alternatively charged lines with line width of approximately 100 nm. Detailed calculations using DLVO theory agree well with the observed long-range interactions and also estimate lateral forces as strong as (1-3) x 10(-7) dyn, which well explains the observed guided placement of Au nanoparticles.

Non-nearest-neighbor jumps in 2D diffusion: Pd on W(110).

A variety of jumps has in the past been identified in diffusion of atoms on 1D channeled surfaces. To establish the jump processes important in diffusion on a 2D surface, the movement of individual Pd atoms has been examined on W(110). From the distribution of displacements of Pd at high temperatures, double jumps are found along the close-packed <111>. For the first time, sizable differences are also observed between the mean-square displacements along x and y, which demonstrate unexpected contributions from jumps along <110>, but not along <001>. These jumps proceed over activation barriers higher than for single jumps, under conditions predicted from previous work with Pd on the channeled W(211).