Gate-defined quantum point contacts in a germanium quantum well.

We report an experimental study of quantum point contacts defined in a high-quality strained germanium quantum well with layered electric gates. At a zero magnetic field, we observed quantized conductance plateaus in units of 2e2/h. Bias-spectroscopy measurements reveal that the energy spacing between successive one-dimensional subbands ranges from 1.5 to 5 meV as a consequence of the small effective mass of the holes and the narrow gate constrictions. At finite magnetic fields perpendicular to the device plane, the edges of the conductance plateaus get split due to the Zeeman effect and Landé g factors were estimated to be ∼6.6 for the holes in the germanium quantum well. We demonstrate that all quantum point contacts in the same device have comparable performances, indicating a reliable and reproducible device fabrication process. Thus, our work lays a foundation for investigating multiple forefronts of physics in germanium-based quantum devices that require quantum point contacts as building blocks.

High-performance GeSi/Ge multi-quantum well photodetector on a Ge-buffered Si substrate.

This work demonstrates a high-performance photodetector with a 4-cycle Ge0.86Si0.14/Ge multi-quantum well (MQW) structure grown by reduced pressure chemical vapor deposition techniques on a Ge-buffered Si (100) substrate. At -1 V bias, the dark current density of the fabricated PIN mesa devices is as low as 3 mA/cm2, and the optical responsivities are 0.51 and 0.17 A/W at 1310 and 1550 nm, respectively, corresponding to the cutoff wavelength of 1620 nm. At the same time, the device has good high-power performance and continuous repeatable light response. On the other hand, the temperature coefficient of resistance (TCR) of the device is as high as -5.18%/K, surpassing all commercial thermal detectors. These results indicate that the CMOS-compatible and low-cost Ge0.86Si0.14/Ge multilayer structure is promising for short-wave infrared and uncooled infrared imaging.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Design Strategy of High Stability Vertically Aligned RGO@V2O5 Heterostructure Cathodes for Flexible Quasi-Solid-State Aqueous Zinc-Ion Batteries.

Among various cathodes for aqueous zinc-ion batteries (AZIBs), vanadium-based oxides have garnered significant attention in research circles owing to their exceptionally high theoretical specific capacity. However, the outstanding zinc storage capacity of vanadium pentoxide is constrained by its irreversible dissolution in an aqueous solution. Here, we propose a laser reduction of graphene oxide and construct a heterostructure of V2O5 coated with vertically aligned reduced graphene oxide (VrGO). The VrGO nanosheets effectively suppress the dissolution of V2O5 and provide channels for the efficient transport of zinc ions and electrons, so the electrochemical reaction kinetics of the electrode are improved. The AZIB based on the VrGO@V2O5 heterostructure cathode has a high specific capacity of 254.9 mAh g-1 at 0.2 A g-1 and excellent cycle stability with a capacity retention rate of 90.1% after 5000 cycles of charge and discharge. When assembled into a flexible quasi-solid-state AZIB, the capacity of the device is reduced by only 2% after 1000 bending cycles, showing good potential for wearable applications. This work provides a reliable strategy for designing flexible AZIB with high electrochemical performance and structural stability.

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions.

SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiH2Cl2, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated. The interface quality was characterized by transmission electron microscopy/atomic force microscopy/high-resolution X-ray diffraction methods. It was observed that limiting the migration of Ge atoms in the interface was critical for optimizing a sharp interface, and the addition of DCS was found to decrease the interface transition thickness. The change of the interfacial transition layer is not significant in the short treatment time of HCl. When the processing time of HCl is increased, the internal interface is optimized to a certain extent but the corresponding film thickness is also reduced. This study provides technical support for the acquisition of an abrupt interface and will have a very favorable influence on the performance improvement of miniaturized devices in the future.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 µA/µm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process.

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control". A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an "exposed top" structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

Undoped Strained Ge Quantum Well with Ultrahigh Mobility of Two Million.

We develop a method to fabricate an undoped Ge quantum well (QW) under a 32 nm relaxed Si0.2Ge0.8 shallow barrier. The bottom barrier contains Si0.2Ge0.8 (650 °C) and Si0.1Ge0.9 (800 °C) such that variation of Ge content forms a sharp interface that can suppress the threading dislocation density (TDD) penetrating into the undoped Ge quantum well. The SiGe barrier introduces enough in-plane parallel strain (ε∥ strain -0.41%) in the Ge quantum well. The heterostructure field-effect transistors with a shallow buried channel obtain an ultrahigh two-dimensional hole gas (2DHG) mobility over 2 × 106 cm2/(V s) and a very low percolation density of (5.689 ± 0.062) × 1010 cm-2. The fractional indication is also observed at high density and high magnetic fields. This strained germanium as a noise mitigation material provides a platform for integration of quantum computation with a long coherence time and fast all-electrical manipulation.

Successful treatment of a severe Takotsubo syndrome case complicated by liver abscess.

The main manifestations of Takotsubo syndrome (TTS) are a spherical expansion of the left ventricle or near the apex and decreased systolic function. TTS is mostly thought to be induced by emotional stress, and the induction of TTS by severe infection is not often reported. A 72-year-old female patient with liver abscess reported herein was admitted due to repeated fever with a history of hypertension and impaired glucose tolerance. Her severe infection caused TTS, and her blood pressure dropped to 80/40 mmHg. IABP treatment was performed immediately and continued for 10 days, and comprehensive medication was administered. Based on her disease course and her smooth recovery, general insights and learnings may be: Adding to mental and other pathological stress reaction, serious infections from pathogenic microorganism could be of great important causation of stress reaction leading to TTS, while basic diseases such as coronary heart disease, hypertension, and diabetes were be of promoting factors; In addition to effective drug therapies for TTS, the importance of the timely using of IABP should be emphasized.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm-2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 µm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-µm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III-V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.

Esophagogastric junctional neuroendocrine tumor with adenocarcinoma: A case report.

BACKGROUND: At present, cases of esophageal neuroendocrine tumors combined with cardia adenocarcinoma are extremely rare worldwide, and there are no clinical reports. Herein, we describe such a case for clinical reference. CASE SUMMARY: The presence of cardia cancer and esophageal neuroendocrine tumors in a single patient has not yet been reported. The patient in this case underwent prompt endoscopic treatment and additional surgical resection. Pathology revealed the following: The distance between the cardia cancer and the esophageal neuroendocrine tumors was small, approximately 3 mm. Vascular invasion was observed. The esophageal neuroendocrine tumor was determined to be grade G3. According to the treatment guidelines, after the patient received an explanation of their condition, additional surgical procedures were provided in a timely manner. Early detection and early treatment can successfully prolong survival and improve the quality of life of patients. CONCLUSION: Early detection and early treatment can successfully prolong survival and improve the quality of life of such patients.

Manipulating Cation Exchange Reactions in Cu2-xS Nanoparticles via Crystal Structure Transformation.

Copper-deficient Cu2-xS nanoparticles (NPs) are extensively exploited as a superior cation exchange (CE) template to yield sophisticated nanostructures. Recently, it has been discovered that their CE reactions can be facilely manipulated by copper vacancy density, morphology, and NP size. However, the structural similarity of usually utilized Cu2-xS somewhat limits the manipulation of the CE reactions through the factor of crystal structure because it can strongly influence the process of the reaction. Herein, we report a methodology of crystal structure transformation to manipulate the CE reactions. Particularly, roxbyite Cu1.8S nanodisks (NDs) were converted into solid wurtzite CdS NDs and Janus-type Cu1.94S/CdS NDs by a "full"/partial CE reaction with Cd2+. Afterward, the roxbyite Cu1.8S were pseudomorphically transformed into covellite CuS NDs. Unlike Cu1.8S, the CuS was scarcely exchanged because of the unique disulfide (S-S) bonds and converted into hollow wurtzite CdS under a more reactive condition. The S-S bonds were gradually split and CuS@CdS core@shell-type NDs were generated. Therefore, our findings in the present study provide not only a versatile technique to manipulate CE reactions in Cu2-xS NPs but also a better comprehension of their reaction dynamics and pathways.

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm-2 in a globally grown Ge layer to 3.2 × 105 cm-2 for a single-step SEG and to 2.84 × 105 cm-2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications.

GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285-320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

Crystal structure dependent cation exchange reactions in Cu2-xS nanoparticles.

Because of high mobility of Cu+ in crystal lattice, Cu2-xS nanoparticles (NPs) utilized as cation exchange (CE) templates to produce complicated nanomaterials has been extensively investigated. Nevertheless, the structural similarity of commonly used Cu2-xS somewhat limits the exploration of crystal structure dependent CE reactions, since it may dramatically affect the reaction dynamics and pathways. Herein, we select djurleite Cu1.94S and covellite CuS nanodisks (NDs) as starting templates and show that the crystal structure has a strong effect on their CE reactions. In the case of djurleite Cu1.94S NDs, the Cu+ was immediately substituted by Cd2+ and solid wurtzite CdS NDs were produced. At a lower reaction temperature, these NDs were partially substituted, giving rise to the formation of Janus-type Cu1.94S/CdS NDs, and this process is kinetically and thermodynamically favorable. For covellite CuS NDs, they were transformed into hollow CdS NDs under a more aggressive reaction condition due to the unique disulfide covalent bonds. These disulfide bonds distributed along [0 0 1] direction were gradually ruptured/reduced and CuS@CdS core-shell NDs could be obtained. Our findings suggest that not only the CE reaction kinetics and thermodynamics, but also the intermediates and final products are intimately correlated to the crystal structure of the host material.