Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability.

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ∼1.2 µA µm-1 along with a longer retention time (RT) of ∼1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors.

In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade-1) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.

Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications.

In the present work, we demonstrate the potential of double gate junctionless (JL) architecture for enhanced sensitivity for detecting biomolecules in cavity modulated field effect transistors (FETs). The higher values of body factor, achieved in asymmetric gate operation under impact ionization is utilized for enhanced sensing margin which is nearly five times higher than compared to symmetrical mode operation. The intrinsic detection sensitivity is evaluated in terms of threshold voltage change, and the ratio of drain current in the presence and absence of biomolecules in JL nanotransistors. It is shown that asymmetric mode JL transistor achieves a higher degree of detection sensitivity even for a partially filled cavity. The work demonstrates the potential of JL channel architecture for cavity based dielectric modulated FET biosensors.