Designing with relaxed skin tension line in perforator-based island flap for sacral sore reconstruction: A STROBE-compliant observational study.

Many various types of operative techniques have been performed used to treat make-up for sacral defects. Perforator-based flaps with flap transposition, but achieving an optimal flap design and tension-free flap closure without skeletonizing the perforator requires a great deal of clinical experience. In this study, we demonstrate perforator selection based on considerations of the relaxed skin tension line (RSTL), which has proven to be a suitable method of achieving an efficient flap design that enables primary closure. Twenty-five perforator-based flap procedures were performed on 25 patients at a single institution from February 2018 to January 2021. The medical records of patients were retrospectively reviewed. Twenty-three flaps survived completely. Two flaps developed partial tip necrosis but recovered after secondary healing, and 1 patient developed temporary congestion, which resolved spontaneously. No recipient or donor site recurrence or dehiscence was identified during follow-up. We report our clinical experiences of perforator-based flap use in the sacral region. When selecting an appropriate perforating vessel, 2 important points should be considered, that is, a flap long axis parallel to RSTLs and defect shape. According to the method presented in this paper, perforator-based flaps can be transposed safely and easily with few complications and serve as useful practice models to cover sacral defects.

ACE: ARIA-CTR Encryption for Low-End Embedded Processors.

In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard's RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.

Fast Number Theoretic Transform for Ring-LWE on 8-bit AVR Embedded Processor.

In this paper, we optimized Number Theoretic Transform (NTT) and random sampling operations on low-end 8-bit AVR microcontrollers. We focused on the optimized modular multiplication with secure countermeasure (i.e., constant timing), which ensures high performance and prevents timing attack and simple power analysis. In particular, we presented combined Look-Up Table (LUT)-based fast reduction techniques in a regular fashion. This novel approach only requires two times of LUT access to perform the whole modular reduction routine. The implementation is carefully written in assembly language, which reduces the number of memory access and function call routines. With LUT-based optimization techniques, proposed NTT implementations outperform the previous best results by 9.0% and 14.6% for 128-bit security level and 256-bit security level, respectively. Furthermore, we adopted the most optimized AES software implementation to improve the performance of pseudo random number generation for random sampling operation. The encryption of AES-256 counter (CTR) mode used for random number generator requires only 3184 clock cycles for 128-bit data input, which is 9.5% faster than previous state-of-art results. Finally, proposed methods are applied to the whole process of Ring-LWE key scheduling and encryption operations, which require only 524,211 and 659,603 clock cycles for 128-bit security level, respectively. For the key generation of 256-bit security level, 1,325,171 and 1,775,475 clock cycles are required for H/W and S/W AES-based implementations, respectively. For the encryption of 256-bit security level, 1,430,601 and 2,042,474 clock cycles are required for H/W and S/W AES-based implementations, respectively.